UPD784907 Datasheet, PDF (80/98 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLER

µPD784907, 784908
Clock Output Operation (TA = –40 to +85°C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
CLKOUT cycle time
CLKOUT low-level width
CLKOUT high-levell width
CLKOUT rising time
CLKOUT falling time
tCYCL
tCLL
tCLH
tCLR
tCLF
nT
VDD = 4.0 to 5.5 V, 0.5T – 10
0.5T – 20
VDD = 4.0 to 5.5 V, 0.5T – 10
0.5T – 20
VDD = 4.0 to 5.5 V
VDD = 3.5 to 4.0 V
VDD = 4.0 to 5.5 V
VDD = 3.5 to 4.0 V
79
32,000
ns
30
ns
20
ns
30
ns
20
ns
10
ns
0.3
20
ns
10
ns
0.3
20
ns
Remark n: Dividing ratio set by software in the CPU (n = 1, 2, 4, 8, and 16)
T: tCYK (system clock cycle time)
Other Operations (TA = –40 to +85°C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
NMI low-level width
tWNIL
10
NMI high-level width
tWNIH
10
INTP0 low-level width
tWIT0L
4tCYSMP
INTP0 high-level width
tWIT0H
4tCYSMP
INTP1 to INTP3 and CI
low-level width
tWIT1L
4tCYCPU
INTP1 to INTP3 and CI
high-level width
tWIT1H
4tCYCPU
INTP4 and INTP5 low-level width tWIT2L
10
INTP4 and INTP5 high-level width tWIT2H
10
RESET low-level width^Note
tWRSL
10
RESET high-level width
tWRSH
10
MAX.
Unit
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
Note When the power is ON, secure the oscillation stabilization wait time with the RESET low-level width.
Remark tCYSMP: sampling clock set by software
tCYCPU: CPU operation clock set by software in the CPU
80
Data Sheet U11680EJ2V0DS00