UPD784907 Datasheet, PDF (78/98 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLER

µPD784907, 784908
Serial Operation (TA = –40 to +85°C, VDD = 3.5 to 5.5 V, AVSS = VSS = 0 V)
(1) CSI, CSI3
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Serial clock cycle time
(SCK0, SCK3)
Serial clock low-level width
(SCK0, SCK3)
Serial clock high-level width
(SCK0, SCK3)
SI0, SI3 setup time
(to SCK0, SCK3↑)
SI0, SI3 hold time
(from SCK0, SCK3↑)
SO0, SO3 output delay time
(from SCK0, SCK3↓)
SO0, SO3 output hold time
(from SCK0, SCK3↑)
tCYSK0
tWSKL0
tWSKH0
tSSSK0
tHSSK0
tDSBSK1
tDSBSK2
tHSBSK
Input fCLK = fXX
8/fXX
ns
Except fCLK = fXX
4/fCLK
ns
Output Except fCLK = fXX/8
8/fXX
ns
fCLK = fXX/8
16/fXX
ns
Input fCLK = fXX
4/fXX – 40
ns
Except fCLK = fXX
2/fCLK – 40
Output Except fCLK = fXX/8
4/fXX – 40
µs
fCLK = fXX/8
8/fXX – 40
Input fCLK = fXX
4/fXX – 40
ns
Except fCLK = fXX
2/fCLK – 40
Output Except fCLK = fXX/8
4/fXX – 40
µs
fCLK = fXX/8
8/fXX – 40
80
ns
External clock
1/fCLK + 80
ns
Internal clock
80
CMOS push-pull output External clock
0
1/fCLK + 150 ns
Internal clock
0
150
ns
Open-drain output
RL = 1 kΩ
External clock
0
Internal clock
0
1/fCLK + 400 ns
400
ns
When data is transferred
0.5tCYSK0 – 40
ns
Remarks 1. The values in this table are those when fXX = 12.58 MHz, CL = 100 pF.
2. fCLK: system clock frequency (selectable from fXX, fXX/2, fXX/4, and fXX/8 by the standby control
register (STBC))
3. fXX: oscillation frequency (fXX = 12.58 MHz or fXX = 6.29 MHz)
78
Data Sheet U11680EJ2V0DS00