UPD784907 Datasheet, PDF (61/98 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLER

µPD784907, 784908
10.3 Programmable Wait
When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space
while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even when
memory devices having different access times are connected.
In addition, an address wait function that extends the ASTB signal active period is provided to ensure the lapse
of the address decode time. (This function is set for the entire space.)
10.4 Pseudo-Static RAM Refresh Function
Refresh is performed as follows:
• Pulse refresh
A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular intervals. When the memory
space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the
REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal
memory access.
• Power-down self-refresh
In standby mode, a low-level signal is output on the REFRQ pin to maintain the contents of pseudo-static RAM.
10.5 Bus Hold Function
A bus hold function is provided to facilitate connection to devices such as a DMA controller. When a bus hold request
signal (HLDRQ) is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and
WR pins enter the high-impedance state, the bus hold acknowledge signal (HLDAK) is made active, and the bus is
released to the external bus master as soon as the current bus cycle is completed.
While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.
Data Sheet U11680EJ2V0DS00
61