UPD784907 Datasheet, PDF (79/98 Pages) NEC – 16-BIT SINGLE-CHIP MICROCONTROLLER

µPD784907, 784908
(2) IOE1, IOE2 (TA = –40 to +85°C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Serial clock cycle time
tCYSK1
Input VDD = 4.0 to 5.5 V
640
ns
(SCK1, SCK2)
1,280
ns
Output Internal, divided by 8
T
ns
Serial clock low-level width
tWSKL1
Input VDD = 4.0 to 5.5 V
280
ns
(SCK1, SCK2)
600
ns
Output Internal, divided by 8
0.5T – 40
ns
Serial clock high-level width
tWSKH1
Input VDD = 4.0 to 5.5 V
280
ns
(SCK1, SCK2)
600
ns
Output Internal, divided by 8
0.5T – 40
ns
SI1, SI2 setup time
(to SCK1, SCK2↑)
tSSSK1
40
ns
SI1, SI2 hold time
(from SCK1, SCK2↑)
tHSSK1
40
ns
SO1, SO2 output delay time
(from SCK1, SCK2↑)
tDSOSK
0
50
ns
SO1, SO2 output hold time
tHSOSK
When data is transferred
0.5tCYSK1 – 40
ns
(from SCK1, SCK2↑)
Remarks 1. The values in this table are those when CL = 100 pF.
2. T: serial clock cycle set by software. The minimum value is 8/fXX.
(3) UART, UART2 (TA = –40 to +85°C, VDD = AVDD = 3.5 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Symbol
Conditions
MIN.
ASCK clock input cycle time
tCYASK
VDD = 4.5 to 5.5 V
160
320
ASCK clock low-level width
tWASKL
VDD = 4.5 to 5.5 V
65
120
ASCK clock high-level width
tWASKH
VDD = 4.5 to 5.5 V
65
120
MAX.
Unit
ns
ns
ns
ns
ns
ns
Data Sheet U11680EJ2V0DS00
79