UPD784218 Datasheet, PDF (72/92 Pages) NEC – 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS

µPD784218, 784218Y
(d) I²C bus mode (µPD784218Y only)
Parameter
Symbol
Standard Mode
High-Speed Mode
Unit
MIN.
MAX.
MIN.
MAX.
SCL0 clock frequency
fCLK
0
100
0
400
kHz
Bus free time (between stop
tBUF
4.7
and start conditions)
Hold time^Note1
tHD : STA
4.0
––
1.3
––
µs
––
0.6
––
µs
Low-level width of SCL0 clock tLOW
4.7
––
1.3
––
µs
High-level width of SCL0 clock tHIGH
4.0
––
0.6
––
µs
Setup time of start/restart
tSU : STA
4.7
conditions
––
0.6
––
µs
Data
hold
time
When using CBUS-
compatible master
When using I²C bus
tHD : DAT
Data setup time
tSU : DAT
Rise time of SDA0 and SCL0
tR
signals
Fall time of SDA0 and SCL0
tF
signals
5.0
0^{Note 2}
250
––
––
––
––
––
µs
––
0^{Note 2}
0.9^{Note 3}
µs
––
100^{Note 4}
––
ns
1,000
20 + 0.1Cb^{Note 5}
300
ns
300
20 + 0.1Cb^{Note 5}
300
ns
Setup time of stop condition tSU : STO
4.0
––
0.6
––
µs
Pulse width of spike restricted tSP
––
by input filter
––
0
50
ns
Load capacitance of each bus Cb
––
400
––
400
pF
line
Notes 1. For the start condition, the first clock pulse is generated after the hold time.
2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal
SDA0 signal (on VIHmin.) with at least 300 ns of hold time.
3. If the device does not extend the SCL0 signal low hold time (tLOW), only maximum data hold time
tHD : DAT needs to be satisfied.
4. The high-speed mode I²C bus can be used in a standard mode I²C bus system. In this case, the
conditions described below must be satisfied.
• If the device does not extend the SCL0 signal low state hold time
tSU : DAT ≥ 250 ns
• If the device extends the SCL0 signal low state hold time
Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released
(tRmax. + tSU : DAT = 1,250 ns by standard mode I²C bus specification)
5. Cb: total capacitance per one bus line (unit: pF)
72
Data Sheet U12304EJ2V0DS00