UPD784218 Datasheet, PDF (68/92 Pages) NEC – 16-/8-BIT SINGLE-CHIP MICROCONTROLLERS

µPD784218, 784218Y
AC Characteristics (TA = –40 to +85°C, VDD = AVDD = 2.2 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Conditions
MIN.
Cycle time
tCYK 4.5 V ≤ VDD ≤ 5.5 V
80
2.7 V ≤ VDD < 4.5 V
160
2.2 V ≤ VDD < 2.7 V
320
Address setup time (to ASTB↓) tSAST VDD = 5.0 V
(0.5 + a) T – 11
VDD = 3.0 V
(0.5 + a) T – 15
Address hold time (from ASTB↓) tHSTLA VDD = 5.0 V
0.5T – 19
VDD = 3.0 V
0.5T – 24
ASTB high-level width
tWSTH VDD = 5.0 V
(0.5 + a) T – 17
VDD = 3.0 V
(0.5 + a) T – 40
Address hold time (from RD↑)
tHRA VDD = 5.0 V
0.5T – 14
VDD = 3.0 V
0.5T – 14
Delay time from address to RD↓ tDAR VDD = 5.0 V
(1 + a) T – 24
VDD = 3.0 V
(1 + a) T – 24
Address float time (from RD↓)
tFRA
0
Data input time from address
tDAID VDD = 5.0 V
VDD = 3.0 V
Data input time from ASTB↓
tDSTID VDD = 5.0 V
VDD = 3.0 V
Data input time from RD↓
tDRID VDD = 5.0 V
VDD = 3.0 V
Delay time from ASTB↓ to RD↓ tDSTR VDD = 5.0 V
0.5T – 9
VDD = 3.0 V
0.5T – 9
Data hold time (from RD↑)
tHRID
0
Address active time from RD↑
tDRA VDD = 5.0 V
0.5T – 2
VDD = 3.0 V
0.5T – 12
Delay time from RD↑ to ASTB↑ tDRST VDD = 5.0 V
0.5T – 9
VDD = 3.0 V
0.5T – 9
RD low-level width
tWRL VDD = 5.0 V
(1.5 + n) T – 25
VDD = 3.0 V
(1.5 + n) T – 30
Delay time from address to WR↓ tDAW VDD = 5.0 V
(1 + a) T – 24
VDD = 3.0 V
(1 + a) T – 24
Address hold time (from WR↑)
tHWA VDD = 5.0 V
0.5T – 14
VDD = 3.0 V
0.5T – 14
Delay time from ASTB↓ to data
output
tDSTOD
VDD = 5.0 V
VDD = 3.0 V
Remark T: tCYK = 1/fXX (fXX: main system clock frequency)
a: 1 (during address wait), otherwise 0
n: Number of waits (n ≥ 0)
68
Data Sheet U12304EJ2V0DS00
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2.5 + a + n) T – 37 ns
(2.5 + a + n) T – 52 ns
(2 + n) T – 35 ns
(2 + n) T – 50 ns
(1.5 + n) T – 40 ns
(1.5 + n) T – 50 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.5T + 15
ns
0.5T + 20
ns