UPD78361A Datasheet, PDF (69/88 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCONTROLLER

µPD78361A, 78362A
AC Characteristics (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V, CL = 100 pF, fXX = 8 MHz)
System Clock Cycle
Parameter
System clock cycle time
Symbol
tCYK
Test conditions
MIN. MAX. Unit
62.5 166.7
ns
Serial Operation (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V)
Parameter
Serial clock cycle time
Symbol
tCYSK
Serial clock low-level
width
tWSKL
Serial clock high-level
width
tWSKH
SI setup time (vs. SCK ↑)
SI hold time (vs. SCK ↑)
SCK ↓ → SO delay time
tSRXSK
tHSKRX
tDSKTX
SCK output
SCK input
SCK output
SCK input
SCK output
SCK input
Test conditions
Internal 8 dividing
External clock
Internal 8 dividing
External clock
Internal 8 dividing
External clock
R = 1 kΩ, C = 100 pF
MIN. MAX. Unit
500
ns
500
ns
210
ns
210
ns
210
ns
210
ns
80
ns
80
ns
210
ns
Up/Down Counter Operation (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V)
Parameter
Symbol
Test conditions
TIUD high-/low-level
width
tWTIUH, tWTIUL Other than mode 4
Mode 4
TCUD high-/low-level
width
tWTCUH, tWTCUL Other than mode 4
Mode 4
TCLRUD high-/low-level width tWCLUH, tWCLUL
TCUD setup time (vs. TIUD ↑) tSTCU Mode 3
TCUD hold time (vs. TIUD ↑) tHTCU Mode 3
TIUD setup time (vs. TCUD) tS4TIU Mode 4
TIUD hold time (vs. TCUD) tH4TIU Mode 4
TIUD & TCUD cycle time tCYC
Other than mode 4
tCYC4
Mode 4
MIN.
2T
4T
2T
4T
2T
T
T
2T
2T
MAX.
4
2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
Remark T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.)
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