UPD78361A Datasheet, PDF (28/88 Pages) NEC – 16/8-BIT SINGLE-CHIP MICROCONTROLLER

µPD78361A, 78362A
3.5 CLOCK GENERATOR CIRCUIT
The clock generator circuit generates and controls the internal system clock (CLK) that is supplied to the CPU.
Figure 3-2. Block Diagram of Clock Generator Circuit
X1 _System
cloock
oscillator
circuit
X2
Frequency
Frequency
divider
divider
f XX
or
1/2
fX
PLL
control
circuit
1/2
f CLK
Internal system
clock (CLK)
STOP mode
Remarks 1.
2.
3.
fXX : crystal oscillation frequency
fX : external clock frequency
fCLK: internal system clock frequency
By connecting an 8-MHz crystal resonator across the X1 and X2 pins, an internal system clock of up to 16
MHz (fCLK) can be generated.
The system clock oscillation circuit oscillates by using the crystal resonator connected across the X1 and
X2 pins. It stops oscillation in standby mode.
An external clock can also be input. To do so, input the clock signal to the X1 pin and leave the X2 pin open.
Caution Do not set STOP mode when the external clock is used.
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