MCF5272 Datasheet, PDF (70/550 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

Features and Enhancements
• Two-stage IFP (plus optional instruction buffer stage)
— Instruction address generation (IAG) calculates the next prefetch address.
— Instruction fetch cycle (IC) initiates prefetch on the processor’s local instruction
bus.
— Instruction buffer (IB) optional stage uses FIFO queue to minimize effects of
fetch latency.
• Two-stage OEP
— Decode, select/operand fetch (DSOC) decodes the instruction and selects the
required components for the effective address calculation, or the operand fetch
cycle.
— Address generation/execute (AGEX) calculates the operand address, or performs
the execution of the instruction.
Instruction
IAG
Address
Generation
IC
Instruction
Fetch
Pipeline
Instruction
Fetch Cycle
IB
FIFO
Instruction Buffer
Address [31:0]
Operand
DSOC
Decode & Select,
Operand Fetch
Execution
Pipeline
AGEX
Address
Generation,
Execute
Data[31:0]
Figure 2-1. ColdFire Pipeline
2.1.1.1 Instruction Fetch Pipeline (IFP)
The IFP generates instruction addresses and fetches. Because the fetch and execution
pipelines are decoupled by a 3 longword FIFO buffer, the IFP can prefetch instructions
before the OEP needs them, minimizing stalls.
2-2
MCF5272 User’s Manual
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