MCF5272 Datasheet, PDF (543/550 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

PWM
control register, 18-3
operation, 18-2
overview, 18-1
programming model, 18-2
width register, 18-4
Q
QSPI
address register, 14-14
baud rate selection, 14-6
command RAM bit description, 14-14
data register, 14-14
delay register, 14-11
interrupt, 14-12
mode register, 14-9
module description, 14-1
operation, 14-3
overview and features, 14-1
programming
example, 14-15
model, 14-9
RAM
command, 14-6
model, 14-4
receive, 14-5
transmit, 14-6
slave bus interface, 14-3
transfer
data, 14-8
delays, 14-7
length, 14-8
wrap register, 14-12
R
RAM
QSPI command bit description, 14-14
USB configuration, 12-26, 12-28
RAM base address registers, 2-10
RAMBAR
overview, 4-3
power management programming, 4-5
Read/write, bus, 20-2
Registers
A0–A6, 2-6
A7, 2-7
AATR, 5-7
ABLR/ABHR, 5-6, 5-8
access control, 2-10, 4-15
activate low-power, 6-10
address, 2-6
address (A0 – A6), 2-6
ALPR, 6-10
MOTOROLA
INDEX
B2 data transmit, 13-17
BI data receive, 13-15
cache configuration, 2-9
cache control, 4-13
CACR, 2-9
CCR, 2-7
chip select
base, 8-3
general, 8-2
option, 8-5
condition code, 2-7, 2-7
condition code (CCR), 2-7
CSBR, 8-3
CSOR, 8-5
CSR, 5-9
D data receive, 13-16
D0–D7, 2-6
data, 2-6
data breakpoint/mask, 5-11
data D0 - D7, 2-6
DBCR, 10-6
D-Channel request, 13-31
DDAR, 10-6
debug attribute trigger, 5-7
descriptor active, 11-15
device identification, 6-11
DIR, 10-4
DMA
byte count, 10-6
controller, 10-2
destination address, 10-6
interrupt, 10-4
mode, 10-2
sourse address, 10-5
DMR, 10-2
DSAR, 10-5
Ethernet control, 11-12
FIFO
receive bound, 11-19
receive start, 11-20
transmit start, 11-22
GCI
C/I channel transmit status, 13-29
monitor channel transmit abort, 13-26
GPIO
control port, 17-2–17-8
data, 17-11
data direction, 17-10
hash table
high, 11-27
low, 11-27
IDCODE, 6-11
integer data formats in, 2-11
interrupt
event, 11-12
Index
Index-5