MCF5272 Datasheet, PDF (368/550 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

Register Descriptions
Table 16-4 describes USRn fields.
Table 16-4. USRn Field Descriptions
Bits Name
Description
7
RB Received break. The received break circuit detects breaks that originate in the middle of a received
character. However, a break in the middle of a character must persist until the end of the next
detected character time.
0 No break was received.
1 An all-zero character of the programmed length was received without a stop bit. RB is valid only
when RxRDY = 1. Only a single FIFO position is occupied when a break is received. Further
entries to the FIFO are inhibited until RxD returns to the high state for at least one-half bit time,
which is equal to two successive edges of the UART clock.
6
FE Framing error.
0 No framing error occurred.
1 No stop bit was detected when the corresponding data character in the FIFO was received. The
stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RxRDY = 1.
5
PE Parity error. Valid only if RxRDY = 1.
0 No parity error occurred.
1 If UMR1n[PM] = 0x (with parity or force parity), the corresponding character in the FIFO was
received with incorrect parity. If UMR1n[PM] = 11 (multidrop), PE stores the received A/D bit.
4
OE Overrun error. Indicates whether an overrun occurs.
0 No overrun occurred.
1 One or more characters in the received data stream have been lost. OE is set upon receipt of a
new character when the FIFO is full and a character is already in the shift register waiting for an
empty FIFO position. When this occurs, the character in the receiver shift register and its break
detect, framing error status, and parity error, if any, are lost. OE is cleared by the RESET ERROR
STATUS command in UCRn.
3 TxEMP Transmitter empty.
0 The transmitter buffer is not empty. Either a character is being shifted out, or the transmitter is
disabled. The transmitter is enabled/disabled by programming UCRn[TC].
1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers
are empty). This bit is set after transmission of the last stop bit of a character if there are no
characters in the transmitter holding register awaiting transmission.
2 TxRDY Transmitter ready.
0 The CPU loaded the transmitter holding register or the transmitter is disabled.
1 The transmitter holding register is empty and ready for a character. TxRDY is set when a
character is sent to the transmitter shift register and when the transmitter is first enabled. If the
transmitter is disabled, characters loaded into the transmitter holding register are not sent.
1 FFULL FIFO full. This bit is equivalent to URF[FULL].
0 The FIFO is not full but may hold unread characters.
1 A character was received and the receiver FIFO is now full. Any characters received when the
FIFO is full are lost.
0 RxRDY Receiver ready
0 The CPU has read the receiver buffer and no characters remain in the FIFO after this read.
1 One or more characters were received and are waiting in the receiver buffer FIFO.
16.3.4 UART Clock-Select Registers (UCSRn)
The UART clock-select registers (UCSRn) select an external clock on the URT_CLK input
(divided by 1 or 16) or a prescaled CLKIN as the clocking source for the transmitter and
receiver. See Section 16.5.1, “Transmitter/Receiver Clock Source.” The transmitter and
receiver can use different clock sources. To use CLKIN for both, set UCSRn to 0xDD.
16-8
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