MCF5272 Datasheet, PDF (374/550 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

Register Descriptions
Table 16-9 describes UISRn and UIMRn fields.
Table 16-9. UISRn/UIMRn Field Descriptions
Bits Name
Description
7 COS Change-of-state.
0 UIPCRn[COS] is not selected.
1 Change-of-state occurred on CTS and was programmed in UACRn[IEC] to cause an interrupt.
6 ABC Autobaud calculation.
0 Autobaud is disabled or is waiting for the first receiver character.
1 The baud rate has been calculated and loaded into the clock source divider (UDUn and UDLn).
Once set, this bit is cleared by writing to UCRn[ENAB].
5 RxFIFO Receiver FIFO status. Once set, this bit is cleared by reading URBn.
0 FIFO status indication is disabled or the receiver status has not changed.
1 The receiver status has changed as programmed in URFn[RXS].
4 TxFIFO Transmitter FIFO status. Once set, this bit is cleared by reading UTBn.
0 FIFO status indication is disabled or the transmitter status has not changed.
1 The transmitter status has changed as programmed in UTFn[TXS].
3 RxFTO Receiver FIFO timeout.
0 No receiver FIFO timeout. This bit is cleared by reading all remaining data in the receiver FIFO, by
receiving another character into the FIFO, or if the receiver is disabled. The count to timeout is
restarted when RxFTO is cleared.
1 The receiver FIFO has timed out at 64 baud with unread data below the FIFO fullness level.
2
DB Delta break.
0 No new break-change condition to report. Section 16.3.5, “UART Command Registers (UCRn),”
describes the RESET BREAK-CHANGE INTERRUPT command.
1 The receiver detected the beginning or end of a received break.
1 FFULL/ RxRDY (receiver ready) if UMR1n[FFULL/RxRDY] = 0; FIFO full (FFULL) if UMR1n[FFULL/RxRDY]
RxRDY = 1. Duplicate of USRn[FFULL/RxRDY].
0 TxRDY Transmitter ready. This bit is the duplication of USRn[TxRDY].
0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters
loaded into the transmitter holding register when TxRDY = 0 are not sent.
1 The transmitter holding register is empty and ready to be loaded with a character.
16.3.11 UART Divider Upper/Lower Registers (UDUn/UDLn)
The UDUn registers (formerly called UBG1n) hold the MSB, and the UDLn registers
(formerly UBG2n) hold the LSB of the preload value. UDUn and UDLn concatenate to
provide a divider to CLKIN for transmitter/receiver operation, as described in
Section 16.5.1.2.1, “CLKIN Baud Rates.”
7
0
Field
Divider MSB
Reset
0000_0000
R/W
Write only
Address
MBAR + 0x118 (UDU0), 0x158 (UDU1)
Figure 16-12. UART Divider Upper Registers (UDUn)
16-14
MCF5272 User’s Manual
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