MCF5272 Datasheet, PDF (50/550 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

Terminology Conventions
Table viii. PWM Module Memory Map
MBAR
Offset
Register Name
0x00C0 PWM Control Register 0
0x00C4 PWM Control Register 1
0x00C8 PWM Control Register 2
0x00D0 PWM Pulse Width Register 0
0x00D4 PWM Pulse Width Register 1
0x00D8 PWM Pulse Width Register 2
Old Mnemonic
PWMCR1
PWMCR2
PWMCR3
PWMWD1
PWMWD2
PWMWD3
Table ix. DMA Module Memory Map
MBAR
Offset
Register Name
0x00E0 DMA Mode Register
0x00E6 DMA Interrupt Register
0x00E8 DMA Byte Count Register
0x00EC DMA Source Address Register
0x00F0 DMA Destination Address Register
Old Mnemonic
DCMR
DCIR
DBCR
DSAR
DDAR
Table x. UART0 Module Memory Map
MBAR
Offset
Register Name
0x0100
0x0104
0x0104
0x0108
0x010C
0x010C
0x0110
0x0110
0x0114
0x0114
0x0118
0x011C
0x0120
0x0124
0x0128
0x012C
UART0 Mode Register 1/2
UART0 Status
UART0 Clock Select Register
UART0 Command Register
UART0 Receive Buffer
UART0 Transmit Buffer
UART0 CTS Change Register
UART0 Auxiliary Control Register
UART0 Interrupt Status Register
UART0 Interrupt Mask Register
UART0 Baud Prescaler MSB
UART0 Baud Prescaler LSB
UART0 AutoBaud MSB Register
UART0 AutoBaud LSB Register
UART0 TxFIFO Control/Status Register
UART0 RxFIFO Control/Status Register
Old Mnemonic
U1MR1/U1MR2
U1SR
U1CSR
U1CR
U1RxB
U1TxB
U1CCR
U1ACR
U1ISR
U1IMR
U1BG1
U1BG2
U1ABR1
U1ABR2
U1TxFCSR
U1RxFCSR
New
Mnemonic
PWCR0
PWCR1
PWCR2
PWWD0
PWWD1
PWWD2
New
Mnemonic
No change
No change
No change
No change
No change
New
Mnemonic
U0MR1/U0MR2
U0SR
U0CSR
U0CR
U0RxB
U0TxB
U0CCR
U0ACR
U0ISR
U0IMR
U0BG1
U0BG2
U0ABR1
U0ABR2
U0TxFCSR
U0RxFCSR
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MCF5272 User’s Manual
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