MCF5272 Datasheet, PDF (515/550 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

PLIC Module: IDL and GCI Interface Timing Specifications
Figure 23-17 shows IDL master timings listed in Table 23-17.
P1
DFSC[3:1]
P2
P3
P5
P4
GDCL1_OUT
P7
P6
P8
P9
DOUT1, DOUT3
P10
P11
DIN1, DIN3
Figure 23-17. IDL Master Timing
Table 23-18 lists timing for IDL slave mode.
Table 23-18. IDL Slave Mode Timing, PLIC Ports 0–3
Name
Characteristic
Min Typ Max
Unit
P14 ¹ FSR0, FSR1 period
— 125 —
µs
P15a FSR0 or FSC0 valid before the falling edge of DCL0 (setup time)
25 — —
nS
P22 DCL clock frequency
256 — 4096
Khz
P23 DCL pulse width high
45 — 55 % of DCL period
P24 DCL pulse width low
45 — 55 % of DCL period
P15b FSR1 or FSC1 valid before the falling edge of DCL1 (setup time)
25 — —
nS
P16a DCL0 to FSR0 or FSC0 input Invalid (hold time)
25 — —
nS
P16b DCL1 to FSR1 or FSC1 input Invalid (hold time)
25 — —
nS
P17a Delay from rising edge of DCL0 to low-z and valid data on DOUT0
— — 30
nS
P17b Delay from rising edge of DCL1 to low-z and valid data on DOUT1 and — — 30
nS
DOUT3
P19a Delay from rising edge of DCL0 to high-z on DOUT0
— — 30
nS
P19b Delay from rising edge of DCL1 to high-z on DOUT1 and DOUT3
— — 30
nS
P20 ² Delay from rising edge of DCL1 to DFSC2, DFSC3 Invalid (output hold) 2 — —
nS
P25 Data valid on DIN0 before falling edge of DCL0 (setup time)
25 — —
nS
P25 Data valid on DIN1, DIN3 before falling edge of DCL1 (setup time)
25 — —
nS
P26 Data valid on DIN0 after falling edge of DCL0 (hold time)
25 — —
nS
P26 Data valid on DIN1, DIN3 after falling edge of DCL1 (hold time)
25 — —
nS
1 _{FSR occurs on average every 125 µs.}
2 _{In IDL slave mode, DCL may be any frequency multiple of 8 KHz between 256 KHz and 4.096 MHz inclusive.}
MOTOROLA
Chapter 23. Electrical Characteristics
23-21