MCF5272 Datasheet, PDF (528/550 Pages) Motorola, Inc – MCF5272 ColdFire Integrated Microprocessor Users Manual

List of Memory Map Tables
MBAR
Offset
0x00A0
0x00A4
0x00A8
0x00AC
0x00B0
0x00B4
Table A-7. QSPI Module Memory Map
[31:24]
[23:16]
QSPI Mode Register (QMR)
QSPI Delay Register (QDLYR)
QSPI Wrap Register (QWR)
QSPI Interrupt Register (QIR)
QSPI Address Register (QAR)
QSPI Data Register (QDR)
[15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[7:0]
Table A-8. PWM Module Memory Map
MBAR
Offset
[31:24]
0x00C0 PWM Control Register 1
(PWCR1)
0x00C4 PWM Control Register 2
(PWCR2)
0x00C8 PWM Control Register 3
(PWCR3)
0x00D0
0x00D4
PWM Pulse Width
Register 1 (PWWD1)
PWM Pulse Width
Register 2 (PWWD2)
0x00D8
PWM Pulse Width
Register 3 (PWWD3)
[23:16]
[15:8]
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
[7:0]
MBAR
Offset
0x00E0
0x00E6
0x00E8
0x00EC
0x00F0
Table A-9. DMA Module Memory Map
[31:24]
[23:16]
[15:8]
[7:0]
DMA Mode Register (DCMR)
DMA Interrupt Register (DCIR)
DMA Byte Count Register (DBCR)
DMA Source Address Register (DSAR)
DMA Destination Address Register (DDAR)
Table A-10. UART0 Module Memory Map
MBAR
Offset
0x0100
0x0104
[31:24]
UART0 Mode Register
1/2 (U0MR1/U0MR2)
UART0 Status (U0SR)
[23:16]
[15:8]
Reserved
Reserved
[7:0]
A-4
MCF5272 User’s Manual
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