MMC2080 Datasheet, PDF (6/34 Pages) Motorola, Inc – Integrated Processor with Roaming FLEX Decoder

Features
1.2 Features
The MMC2080/2075 offers the following suite of features.
• M•CORE™ RISC Processor
— 32-bit load/store M•CORE RISC architecture
— Fixed 16-bit instruction length
— 16-entry 32-bit general-purpose register file
— 32-bit internal address and data buses
— Efficient, four-stage, fully interlocked execution pipeline
— Single-cycle execution for most instructions; two cycles for branches and memory accesses
— Special branch, byte, and bit manipulation instructions
— Support for byte, halfword, and word memory accesses
— Fast interrupt support via vectoring/auto-vectoring and a 16-entry dedicated alternate register
file
• Integrated Roaming FLEX alphanumeric decoder (MMC2080 only)
— FLEX paging protocol signal processor
— 1600, 3200, and 6400 bits per second (bps) decoding
— Highly programmable receiver control
— FLEX message fragmentation and group messaging support
— SSID and NID roaming support
— Internal demodulator and data slicer
— Improved battery savings via partial address correlation and intermittent receiver clock
— Full support for revision G1.9 of the FLEX protocol
— External CAP code access through parallel or serial FLASH/PROM
• On-chip memory
— 24 K × 32 CPU ROM (96 K)
— 1.5 K × 32 CPU RAM (6 K)
• On-chip peripherals
— Asynchronous serial communications interface (SCI) with IrDA capability
— Synchronous serial peripheral interface (SPI)
— Frequency synthesizer controller (FSC)
— Melody generator
— 4 × 4 keypad interface
— Multipurpose I/O ports (MPIO)
— Two 16-bit general purpose timers
— Time-of-day (TOD) timer
— Watchdog timer
— Vectored interrupt controller with 16 programmable priority levels
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MMC2080/2075 Technical Data
Preliminary