MMC2080 Datasheet, PDF (33/34 Pages) Motorola, Inc – Integrated Processor with Roaming FLEX Decoder

Electrical Design Considerations
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading
on the case of the package will estimate a junction temperature slightly hotter than the actual temperature.
Hence, the new thermal metric, thermal characterization parameter or Ψ_JT, has been defined to be (T_J - T_T)/
P_D. This value gives a better estimate of the junction temperature in natural convection when using the
surface temperature of the package. Remember that surface temperature readings of packages are subject to
significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat
loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the
top center of the package with thermally conductive epoxy.
NOTE:
Section 3, “Specifications,” on page 28 of this document contains the
package thermal values for this chip.
5.2 Electrical Design Considerations
WARNING:
This device contains protective circuitry to guard against damage due to
high static voltage or electrical fields. However, normal precautions are
advised to avoid application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate logic voltage level (for
example, either Vss or VDD).
Use the following list of recommendations to assure correct operation:
• Provide a low-impedance path from the board power supply to each Vdd pin on the MMC2080/
2075 and from the board ground to each Vss pin.
• Use at least four 0.1 µF bypass capacitors positioned as close as possible to the four sides of the
package to connect the Vdd power source to Vss.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip Vdd and
Vss pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer printed circuit board (PCB) with two inner layers for Vdd and Vss.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the Vdd and Vss circuits.
• All inputs must be terminated (that is, not allowed to float) using CMOS levels.
Take special care to minimize noise levels on the PLL supply pins (both Vdd and Vss).
Design Considerations
33
Preliminary