MMC2080 Datasheet, PDF (24/34 Pages) Motorola, Inc – Integrated Processor with Roaming FLEX Decoder

Tables of Signals
Signal Name
D[31:16]
DVLEB[1:0]
DVL[1:0]
DVLSEL
DVLMX
DSTAT[5:0]
TC[2:0]
TEA
HIGHZ
PULL_EN
SHS
Table 9. Development Extensions (208-Pin Package)
Dir N I/O Cell
Description
I/O N
I/O N
IN
ON
IN
ON
ON
IN
IN
IN
ON
IOHPPH
IOHPPH
INHPP
OTP
INHPP
OTP
OTP
INHPP
INHPP
INHPP
OTP
Extension to provide a 32-bit external bus. The bus is enabled when
either DVL0 or _DVL0 is asserted.
Byte Enable (active low)—Input when BGNT is low; otherwise
output. DVLEB0 enables D[31:24] and DVLEB1 enables D[23:16].
Development Mode—When DVL1 is low, the internal ROM is
bypassed. If the ROM space is addressed when DVL1 is low and
XBOOT is high, the 32-bit extension is enabled and DVLSEL is
asserted to select an external memory.
When DVL0 is low, the 32-bit bus extension is enabled for external
bus masters (BGNT is low) and for debug monitor modes.
Development Select (active low)—When DVL1 is low and XBOOT
is high, this output is asserted when the internal ROM locations are
addressed.
Selects the output of DSTAT[5:0].
When DVLMX is high, DSTAT is the low-order 6 bits of the interrupt
vector. When DVLMX is low, DSTAT[3:0] is the M•CORE pipeline
status, PSTAT[3:0], and DSTAT[5:4] is the transfer size in M•CORE
format.
Processor Transfer Code.
Transfer Error Acknowledge (active low).
Tri-State Disable (active low)—When asserted (low), all tri-state
outputs are disabled (high-z). This performs the same function as
the JTAG HIGHZ command.
Enable Pull-up Resistors—When low, all pull-up resistors (except
the pull-up resistor on this I/O cell) are disabled.
Show Cycle Strobe (active low)— Strobes low when data is valid.
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MMC2080/2075 Technical Data
Preliminary