MC88915TFN55 Datasheet, PDF (5/20 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88915TFN55/70/100/133/160
MC88915TFN55 and MC88915TFN70 (continued)
AC CHARACTERISTICS (TA =–40° C to +85° C, VCC = 5.0V ±5%, Load = 50Ω Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
tRISE/FALL¹
2X_Q Output
tPULSE _WIDTH¹
(Q0–Q4, Q5, Q/2)
tPULSE _WIDTH¹
(2X_Q Output)
tPULSE _WIDTH¹
(2X_Q Output)
Rise/Fall Time, All Outputs
1.0
(Between 0.2VCC and 0.8VCC)
2.5
ns Into a 50Ω Load
Terminated to VCC/2
Rise/Fall Time Into a 20pF Load, With
0.5
Termination Specified in Note ²
1.6
ns tRISE: 0.8V – 2.0V
tFALL: 2.0V – 0.8V
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ VCC/2
0.5tCYCLE – 0.5 ² 0.5tCYCLE + 0.5 ² ns Into a 50Ω Load
Terminated to VCC/2
Output Pulse Width:
2X_Q @ 1.5V
66MHz 0.5tCYCLE – 0.5 ² 0.5tCYCLE + 0.5 ² ns Must Use Termination
50MHz 0.5tCYCLE – 1.0 0.5tCYCLE + 1.0
Specified in Note 2
40MHz 0.5tCYCLE – 1.5 0.5tCYCLE + 1.5
Output Pulse Width:
2X_Q @ VCC/2
50–65MHz 0.5tCYCLE – 1.0 ² 0.5tCYCLE + 1.0 ² ns Into a 50Ω Load
40–49MHz 0.5tCYCLE – 1.5 0.5tCYCLE + 1.5
Terminated to VCC/2
66–70MHz 0.5tCYCLE – 0.5 0.5tCYCLE + 0.5
tPD ^1,3
SYNC Feedback
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
(With 1MΩ from RC1 to An VCC)
–1.05
–0.40
(With 1MΩ from RC1 to An GND)
ns See Note 4 and
Figure 2 for Detailed
Explanation
+1.25
+3.25
tSKEWr ^1,4
Output–to–Output Skew Between Out-
—
(Rising) See Note ⁵ puts Q0–Q4, Q/2 (Rising Edges Only)
tSKEWf ^1,4
Output–to–Output Skew Between Out-
—
(Falling)
puts Q0–Q4 (Falling Edges Only)
tSKEWall^1,4
Output–to–Output Skew 2X_Q, Q/2,
—
Q0–Q4 Rising, Q5 Falling
tLOCK⁵
Time Required to Acquire Phase–Lock
1.0
From Time SYNC Input Signal is
Received
500
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
500
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
750
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
10
ms Also Time to LOCK
Indicator High
tPZL⁶
Output Enable Time OE/RST to 2X_Q,
3.0
Q0–Q4, Q5, and Q/2
14
ns Measured With the
PLL_EN Pin Low
tPHZ,tPLZ⁶
Output Disable Time OE/RST to 2X_Q,
3.0
Q0–Q4, Q5, and Q/2
14
ns Measured With the
PLL_EN Pin Low
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. TCYCLE in this spec is 1/Frequency at which the particular output is running.
3. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is
with C1 = 0.01µF.
6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
reached.
TIMING SOLUTIONS
5
BR1333 — Rev 6
MOTOROLA