MC88915TFN55 Datasheet, PDF (14/20 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88915TFN55/70/100/133/160
6. Calculation of Total Output–to–Skew between
multiple parts (Part–to–Part skew)
By combining the tPD specification and the information in
Note 5, the worst case output–to–output skew between
multiple 88915’s connected in parallel can be calculated.
This calculation assumes that all parts have a common
SYNC input clock with equal delay of that input signal to
each part. This skew value is valid at the 88915 output
pins only (equally loaded), it does not include PCB trace
delays due to varying loads.
With a 1MΩ resistor tied to analog VCC as shown in note
4, the tPD spec. limits between SYNC and the Q/2 output
(connected to the FEEDBACK pin) are –1.05ns and
–0.5ns. To calculate the skew of any given output
between two or more parts, the absolute value of the
distribution of that output given in table 2 must be
subtracted and added to the lower and upper tPD spec
limits respectively. For output Q2, [276 – (–44)] = 320ps is
the absolute value of the distribution. Therefore
–0.50
[–1.05ns – 0.32ns] = –1.37ns is the lower tPD limit, and
[–0.5ns + 0.32ns] = –0.18ns is the upper limit. Therefore
the worst case skew of output Q2 between any number of
parts is |(–1.37) – (–0.18)| = 1.19ns. Q2 has the worst
case skew distribution of any output, so 1.2ns is the
absolute worst case output–to–output skew between
multiple parts.
7. Note 4 explains that the tPD specification was measured
and is guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10MHz. The fixed offset (tPD) as described
above has some dependence on the input frequency and
at what frequency the VCO is running. The graphs of
Figure 3 demonstrate this dependence.
The data presented in Figure 3 is from devices
representing process extremes, and the measurements
were also taken at the voltage extremes (VCC = 5.25V
and 4.75V). Therefore the data in Figure 3 is a realistic
representation of the variation of tPD.
–0.5
–0.75
tPD
SYNC to –1.00
FEEDBACK
(ns)
–1.25
–1.0
tPD
SYNC to
FEEDBACK
(ns)
–1.5
–1.50
2.5
5.0 7.5 10.0 12.5 15.0 17.5
SYNC INPUT FREQUENCY (MHz)
Figure 3a.
tPD versus Frequency Variation for Q/2 Output Fed
Back, Including Process and Voltage Variation @ 25°C
(With 1MΩ Resistor Tied to Analog VCC)
–2.0
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5
SYNC INPUT FREQUENCY (MHz)
Figure 3b.
tPD versus Frequency Variation for Q4 Output Fed
Back, Including Process and Voltage Variation @ 25°C
(With 1MΩ Resistor Tied to Analog VCC)
3.5
3.0
tPD
SYNC to
2.5
FEEDBACK
(ns)
2.0
1.5
1.0
0.5
2.5
3.5
3.0
tPD
SYNC to
2.5
FEEDBACK
(ns) 2.0
1.5
5.0 7.5 10.0 12.5 15.0 17.5
SYNC INPUT FREQUENCY (MHz)
1.0
0.5
0
5
10
15
20
25
SYNC INPUT FREQUENCY (MHz)
Figure 3c.
tPD versus Frequency Variation for Q/2 Output Fed
Back, Including Process and Voltage Variation @ 25°C
(With 1MΩ Resistor Tied to Analog GND)
Figure 3d.
tPD versus Frequency Variation for Q4 Output Fed
Back, Including Process and Voltage Variation @ 25°C
(With 1MΩ Resistor Tied to Analog GND)
MOTOROLA
14
TIMING SOLUTIONS
BR1333 — Rev 6