MC88915TFN55 Datasheet, PDF (13/20 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88915TFN55/70/100/133/160
EXTERNAL LOOP FILTER ^RC1
330Ω _R2
0.1µF
C1
1MΩ
REFERENCE
RESISTOR
ANALOG GND
With the 1MΩ resistor tied in this fashion, the tPD specification
measured at the input pins is:
tPD = 2.25ns ± 1.0ns
SYNC INPUT
2.25ns OFFSET
FEEDBACK OUTPUT
3.0V
5.0V
ANALOG VCC
1MΩ
REFERENCE
RC1
RESISTOR _330Ω
R2
0.1µF
C1
ANALOG GND
With the 1MΩ resistor tied in this fashion, the tPD specification
measured at the input pins is:
tPD = –0.775ns ± 0.275ns
SYNC INPUT
FEEDBACK OUTPUT
3.0V
–0.775ns OFFSET
5.0V
Figure 2. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is
Present When a 1MΩ Resistor is Tied to VCC or Ground
5. The tSKEWr specification guarantees that the rising edges
of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall
within a 500ps window within one part. However, if the
relative position of each output within this window is not
specified, the 500 ps window must be added to each side
of the tPD specification limits to calculate the total
part–to–part skew. For this reason the absolute
Output
Q0
Q1
Q2
Q3
Q4
Q/2
2X_Q
–
(ps)
0
–72
–44
–40
–274
–16
–633
distribution of these outputs are provided in table 2. When
taking the skew data, Q0 was used as a reference, so all
measurements are relative to this output. The information
in Table 2 is derived from measurements taken from the
14 process lots described in Note 1, over the temperature
and voltage range.
+
(ps)
0
40
276
255
–34
250
–35
Table 2. Relative Positions of Outputs Q/2, Q0–Q4, 2X_Q, Within the 500ps tSKEWr Spec Window
TIMING SOLUTIONS
13
BR1333 — Rev 6
MOTOROLA