MC88915TFN55 Datasheet, PDF (15/20 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88915TFN55/70/100/133/160
8. The lock indicator pin (LOCK) will reliably indicate a
phase–locked condition at SYNC input frequencies down
to 10MHz. At frequencies below 10MHz, the frequency of
correction pulses going into the phase detector form the
SYNC and FEEDBACK pins may not be sufficient to allow
the lock indicator circuitry to accurately predict a
phase–locked conditition. The MC88915T is guaranteed
to provide stable phase–locked operation down to the
appropriate minimum input frequency given in Table 1,
even though the LOCK pin may be LOW at frequencies
below 10MHZ. The exact minimum frequency where the
lock indicator functionality can be guaranteed will be
available when the MC88915T reaches ‘MC’ status.
SYNC INPUT
(SYNC[1] or
SYNC[0])
t _PD
tCYCLE SYNC INPUT
FEEDBACK
INPUT
Q/2 OUTPUT
tSKEWALL
Q0 – Q4
OUTPUTS
Q5 OUTPUT
tSKEWf
tSKEWr
tSKEWf
tCYCLE _{“Q” OUTPUTS}
tSKEWR
2X_Q OUTPUT
Figure 4. Output/Input Switching Waveforms and Timing Diagrams
(These waveforms represent the hook–up configuration of Figure 5a on page 16)
Timing Notes:
• The MC88915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does
not require a 50% duty cycle.
• All skew specs are measured between the VCC/2 crossing point of the appropriate output edges.All skews
are specified as ‘windows’, not as a ± deviation around a center point.
• If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency
would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the
Q/2 output would run at half the SYNC frequency.
TIMING SOLUTIONS
15
BR1333 — Rev 6
MOTOROLA