MC88915TFN55 Datasheet, PDF (11/20 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88915TFN55/70/100/133/160
MC88915TFN160 (continued)
AC CHARACTERISTICS (TA =0° C to +70° C, VCC = 5.0V ±5%, Load = 50Ω Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
tRISE/FALL
2X_Q Output
tPULSE _WIDTH
(Q0–Q4, Q5, Q/2)
tPULSE _WIDTH
(2X_Q Output)
Rise/Fall Time, All Outputs
1.0
(Between 0.2VCC and 0.8VCC)
2.5
ns Into a 50Ω Load
Terminated to VCC/2
Rise/Fall Time
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ VCC/2
0.5
1.6
ns tRISE: 0.8V – 2.0V
tFALL: 2.0V – 0.8V
0.5tCYCLE – 0.5 ² 0.5tCYCLE + 0.5 ² ns Into a 50Ω Load
Terminated to VCC/2
Output Pulse Width:
2X_Q @ VCC
80MHz 0.5tCYCLE – 0.7 0.5tCYCLE + 0.7 ns
100MHz 0.5tCYCLE – 0.5 0.5tCYCLE + 0.5
133MHz 0.5tCYCLE – 0.5 0.5tCYCLE + 0.5
160MHz
TBD
TBD
tPD¹
SYNC Feedback
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
133MHz
160MHz
(With 1MΩ from RC1 to An VCC)
–1.05
–0.9
–0.25
–0.10
ns See Note 2 and
Figure 2 for Detailed
Explanation
tCYCLE
(2x_Q Output)
tSKEWr³
(Rising) See Note 4
Cycle–to–Cycle Variation
133MHz
160MHz
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
tCYCLE – 300ps
tCYCLE – 300ps
—
tSKEWf³
(Falling)
Output–to–Output Skew Between Out-
—
puts Q0–Q4 (Falling Edges Only)
tSKEWall³
Output–to–Output Skew 2X_Q, Q/2,
—
Q0–Q4 Rising, Q5 Falling
tLOCK⁴
Time Required to Acquire Phase–Lock
1.0
From Time SYNC Input Signal is
Received
tPZL⁵
Output Enable Time OE/RST to 2X_Q,
3.0
Q0–Q4, Q5, and Q/2
tPHZ,tPLZ⁵
Output Disable Time OE/RST to 2X_Q,
3.0
Q0–Q4, Q5, and Q/2
tCYCLE + 300ps
tCYCLE + 300ps
500
500
750
10
14
14
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
ps All Outputs Into a
Matched 50Ω Load
Terminated to VCC/2
ms Also Time to LOCK
Indicator High
ns Measured With the
PLL_EN Pin Low
ns Measured With the
PLL_EN Pin Low
1. TCYCLE in this spec is 1/Frequency at which the particular output is running.
2. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1µF, tLOCK minimum is
with C1 = 0.01µF.
5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
reached.
TIMING SOLUTIONS
11
BR1333 — Rev 6
MOTOROLA