MC88915TFN55 Datasheet, PDF (12/20 Pages) Motorola, Inc – LOW SKEW CMOS PLL CLOCK DRIVER

MC88915TFN55/70/100/133/160
Applications Information for All Versions
General AC Specification Notes
1. Several specifications can only be measured when the
MC88915TFN55, 70 and 100 are in phase–locked
operation. It is not possible to have the part in phase–lock
on ATE (automated test equipment). Statistical
characterization techniques were used to guarantee
those specifications which cannot be measured on the
ATE. MC88915TFN55, 70 and 100 units were fabricated
with key transistor properties intentionally varied to
create a 14 cell designed experimental matrix. IC
performance was characterized over a range of transistor
properties (represented by the 14 cells) in excess of the
expected process variation of the wafer fabrication area,
to set performance limits of ATE testable specifications
within those which are to be guaranteed by statistical
characterization. In this way all units passing the ATE test
will meet or exceed the non–tested specifications limits.
2. These two specs (tRlSE/FALL and tPULSE Width 2X_Q
output) guarantee that the MC88915T meets the 40MHz
and 33MHz MC68040 P–Clock input specification (at
80MHz and 66MHz, respectively). For these two specs to
be guaranteed by Motorola, the termination scheme
shown below in Figure 1 must be used.
3. The wiring Diagrams and explanations in Figure 5
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a
180° phase shift between the SYNC input and the “Q”
outputs. Table 1 below summarizes the allowable SYNC
frequency range for each possible configuration.
88915
2X_Q
Output
Rs
ZO (CLOCK TRACE)
Rs = Zo – 7 Ω
Rp
68040
P–Clock
Input
Rp = 1.5 Zo
Figure 1. MC68040 P–Clock Input Termination Scheme
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHZ)
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Q/2
Any “Q” (Q0–Q4)
Q5
2X_Q
Q/2
Any “Q” (Q0–Q4)
Q5
2X_Q
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
2.5 to (2X_Q FMAX Spec)/8
5 to (2X_Q FMAX Spec)/4
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
Corresponding VCO
Frequency Range
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAXSpec)
20 to (2X_Q FMAXSpec)
Phase Relationships
of the “Q” Outputs
to Rising SYNC Edge
0°
0°
180°
0°
0°
0°
180°
0°
Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.
4. A 1MΩ resistor tied to either Analog VCC or Analog GND
as shown in Figure 2 is required to ensure no jitter is
present on the MC88915T outputs. This technique
causes a phase offset between the SYNC input and the
output connected to the FEEDBACK input, measured at
the input pins. The tPD spec describes how this offset
varies with process, temperature, and voltage. The specs
were arrived at by measuring the phase relationship for
the 14 lots described in note 1 while the part was in
phase–locked operation. The actual measurements were
made with a 10MHz SYNC input (1.0ns edge rate from
0.8V – 2.0V) with the Q/2 output fed back. The phase
measurements were made at 1.5V. The Q/2 output was
terminated at the FEEDBACK input with 100Ω to VCC and
100Ω to ground.
MOTOROLA
12
TIMING SOLUTIONS
BR1333 — Rev 6