MC68HC11KA4TS Datasheet, PDF (46/68 Pages) Motorola, Inc – 8-Bit Microcontroller

NOTE
This figure shows transmission order when LSBF = 0 default. If LSBF = 1, data is
transferred in reverse order (LSB first).
SPR2, SPR1 and SPR0 — SPI Clock Rate Selects (SPR2 is located in OPT2 register)
SPR[2:0]
000
001
010
011
100
101
110
111
Divide
E Clock By
2
4
16
32
8
16
64
128
Frequency at
E = 2 MHz (Baud)
1.0 MHz
500 kHz
125 kHz
62.5 kHz
250 kHz
125 kHz
31.3 kHz
15.6 kHz
SPSR —Serial Peripheral Status Register
$0029
Bit 7
6
5
4
3
2
1
Bit 0
SPIF WCOL
—
MODF
—
—
—
—
RESET:
0
0
0
0
0
0
0
0
SPIF — SPI Transfer Complete Flag
This flag is set when an SPI transfer is complete (after eight SCK cycles in a data transfer). Clear this
flag by reading SPSR (with SPIF = 1), then access SPDR data register.
0 = No SPI transfer complete or SPI transfer still in progress
1 = SPI transfer complete
WCOL — Write Collision
This flag is set if the MCU tries to write data into SPDR while an SPI data transfer is in progress. Clear
this flag by reading SPSR (WCOL = 1), then access SPDR.
0 = No write collision
1 = Write collision
Bit 5 — Not implemented
Always reads zero
MODF — Mode Fault (Mode fault terminates SPI operation)
0 = No mode fault
1 = Mode fault (SS is pulled low while MSTR = 1)
Bits [3:0] — Not implemented
Always read zero
SPDR —SPI Data
$002A
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
SPI is double buffered in, single buffered out.
MOTOROLA
46
MC68HC11KA4
MC68HC11KA4TS/D