MC68HC11KA4TS Datasheet, PDF (11/68 Pages) Motorola, Inc – 8-Bit Microcontroller

2 Operating Modes and On-Chip Memory
2.1 Operating Modes
In single-chip operating mode, the MC68HC11KA4 is a stand-alone microcontroller with no external ad-
dress or data bus.
In expanded non-multiplexed operating mode, the MCU can access a 64 Kbyte physical address space.
This space includes the same on-chip memory addresses used for single-chip mode, in addition to ad-
dressing capabilities for external peripheral and memory devices. The expansion bus is made up of
ports B, C, and F, and the R/W signal. In expanded operating mode, high order address bits are output
on the port B pins, low order address bits on the port F pins, and the data bus on port C. The R/W pin
controls the direction of data transfer on the port C bus.
Bootstrap mode allows special-purpose programs to be entered into internal RAM. The bootloader pro-
gram uses the serial communications interface (SCI) to read a program of up to 768 bytes into on-chip
RAM. After a four-character delay, or after receiving the character for address $037F ($047F for
MC68HC11KA2), control passes to the loaded program at $0080.
Special test mode is used primarily for factory testing.
2.2 On-Chip Memory
The M68HC11 CPU is capable of addressing a 64 Kbyte range. The INIT, INIT2, and CONFIG registers
control the existence and locations of the registers, RAM, EEPROM, and ROM in the physical 64 Kbyte
memory space. Addressing beyond the 64 Kbyte range is possible using a memory paging scheme in
expanded mode only.
The 128-byte register block originates at $0000 after reset and can be placed at any other 4 Kbyte
boundary ($x000) after reset by writing an appropriate value to the INIT register.
The 768-byte RAM (1024 bytes in the MC68HC11KA2) can be remapped to any 4 Kbyte boundary in
memory.
The RAM in the MC68HC11KA4 is divided into two sections of 128 bytes and 640 bytes. For the
MC68HC11KA4, 128 bytes of the RAM are mapped at $0000–$007F unless the registers are mapped
to this space. If the registers are located in this space, the same 128 bytes of RAM are located at $0300
to $037F.
The RAM in the MC68HC11KA2 is divided into two sections of 128 bytes and 896 bytes. For the
MC68HC11KA2, 128 bytes of the RAM are mapped at $0000–$007F unless the registers are mapped
to this space. If the registers are located in this space, the same 128 bytes of RAM are located at $0300
to $047F.
Remapping is accomplished by writing appropriate values into the two nibbles of the INIT register. Refer
to the register and RAM mapping examples following the MC68HC11KA4 and MC68HC11KA2 memory
maps.
The 640-byte EEPROM is initially located at $0D80 after reset, assuming EEPROM is enabled in the
memory map by the CONFIG register. EEPROM can be placed at any other 4 Kbyte boundary ($xD80)
by writing appropriate values to the INIT2 register.
The ROMAD and ROMON control bits in the CONFIG register control the position and presence of
ROM/EPROM in the memory map. In special test mode, the ROMON bit is forced to zero so that the
ROM/EPROM is removed from the memory map. In single-chip mode, the ROMAD bit is forced to one,
causing the ROM/EPROM to be enabled at $A000–$FFFF ($8000–$FFFF in the MC68HC11KA2). This
guarantees that there will be ROM/EPROM at the vector space.
MC68HC11KA4
MC68HC11KA4TS/D
MOTOROLA
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