MC68HC11KA4TS Datasheet, PDF (35/68 Pages) Motorola, Inc – 8-Bit Microcontroller

DDRD — Data Direction Register for Port D
$0009
RESET:
Bit 7
—
0
6
5
4
3
2
1
Bit 0
—
DDD5
DDD4
DDD3
DDD2 DDD1
DDD0
0
0
0
0
0
0
0
Bits [7:6] —Not implemented
Always read zero
DDD[5:0] — Data Direction for Port D
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
NOTE
When the SPI system is in slave mode, DDD5 has no meaning nor effect. When
the SPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an
error detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI
system is enabled and expects any of bits [4:2] to be an input that bit will be an input
regardless of the state of the associated DDR bit. If any of bits [4:2] are expected
to be outputs that bit will be an output only if the associated DDR bit is set.
PORTE — Port E Data
$000A
Bit 7
6
5
4
3
2
1
Bit 0
PE7*
PE6*
PE5*
PE4*
PE3
PE2
PE1
PE0
RESET:
U
U
U
U
U
U
U
U
Alt. Pin
Func.:
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
*Not bonded on 64-pin version.
PPAR —Port Pull-Up Assignment
$002C
Bit 7
6
5
4
3
2
1
Bit 0
—
—
—
—
HPPUE GPPUE FPPUE BPPUE
RESET:
0
0
0
0
1
1
1
1
Bits [7:4] — Not implemented
Always read zero
xPPUE — Port x Pin Pull-Up Enable
Refer to PAREN bit in CONFIG register discussed in 6 Parallel Input/Output.
0 = Port x pin on-chip pull-up devices disabled
1 = Port x pin on-chip pull-up devices enabled
NOTE
FPPUE and BPPUE do not apply in expanded mode because ports F and B are
address outputs.
MC68HC11KA4
MC68HC11KA4TS/D
MOTOROLA
35