MC68HC11KA4TS Datasheet, PDF (19/68 Pages) Motorola, Inc – 8-Bit Microcontroller

NOCOP — COP System Disable
Resets to programmed value
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
ROMON — ROM/EPROM Enable
In single-chip mode, ROMON is forced to one out of reset. In special test mode, ROMON is forced to
zero out of reset.
0 = ROM/EPROM removed from memory map
1 = ROM/EPROM present in memory map
EEON — EEPROM Enable
0 = EEPROM disabled from memory map
1 = EEPROM present in memory map with location depending on value specified in EE[3:0] in INIT2
OPT2 —System Configuration Options 2
$0038
Bit 7
6
5
4
3
2
1
Bit 0
—
CWOM
—
IRVNE LSBF
SPR2
XDV1
XDV0
RESET:
0
0
0
—
0
0
0
0
Bit 7 — Not implemented
Always reads zero
CWOM — Port C Wired-OR Mode
Refer to 6 Parallel Input/Output.
Bit 5 — Not implemented
Always reads zero
IRVNE — Internal Read Visibility/Not E
Can be written at any time if SMOD = 1. If SMOD = 0, only one write is allowed. In expanded mode,
IRVNE determines whether IRV is on or off. In special test mode, IRVNE is reset to one. In all other
modes, IRVNE is reset to zero.
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out of the external data bus.
In single-chip modes, this bit determines whether the E clock drives out from the chip.
0 = E is driven out from the chip.
1 = E pin is driven low.
Mode
Single Chip
Expanded
Boot
Special Test
IRVNE Out
of Reset
0
0
0
1
E Clock Out of
Reset
On
On
On
On
IRV Out of
Reset
Off
Off
Off
On
IRVNE
Affects Only
E
IRV
E
IRV
IRVNE
Can Be Written
Once
Once
Once
Once
LSBF — SPI LSB First Enable
Refer to 8 Serial Peripheral Interface.
SPR2 — SPI Clock Rate Select
Refer to 8 Serial Peripheral Interface.
MC68HC11KA4
MC68HC11KA4TS/D
MOTOROLA
19