MC68HC11KA4TS Datasheet, PDF (33/68 Pages) Motorola, Inc – 8-Bit Microcontroller

DDRA — Data Direction Register for Port A
$0001
RESET:
Bit 7
DDA7
0
6
DDA6
0
5
DDA5
0
4
DDA4
0
3
DDA3
0
2
DDA2
0
1
DDA1
0
Bit 0
DDA0
0
DDA[7:0] —Data Direction for Port A
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
PORTB —Port B Data
$0004
Bit 7
6
5
4
3
2
1
Bit 0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
S. Chip or
Boot:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
RESET:
U
U
U
U
U
U
U
U
Expan. or
Test: ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8
Reset state is mode dependent. In single-chip or bootstrap modes, port B pins are high impedance in-
puts with selectable internal pull-up resistors. In expanded or test modes, port B pins are high order ad-
dress outputs and PORTB is not in the memory map.
DDRB — Data Direction Register for Port B
$0002
RESET:
Bit 7
DDB7
0
6
DDB6
0
5
DDB5
0
4
DDB4
0
3
DDB3
0
2
DDB2
0
1
DDB1
0
Bit 0
DDB0
0
DDB[7:0] — Data Direction for Port B
0 = Bits set to zero to configure corresponding I/O pin for input only
1 = Bits set to one to configure corresponding I/O pin for output
PORTF — Port F Data
$0005
Bit 7
6
5
4
3
2
1
Bit 0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
S. Chip or
Boot:
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
RESET:
U
U
U
U
U
U
U
U
Expan. or
Test: ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0
Reset state is mode dependent. In single-chip or bootstrap modes, port F pins are high-impedance in-
puts with selectable internal pull-up resistors. In expanded or test modes, port F pins are low order ad-
dress outputs and PORTF is not in the memory map.
MC68HC11KA4
MC68HC11KA4TS/D
MOTOROLA
33