M5M410092BRF Datasheet, PDF(75/204 Page) Mitsubishi Electric Semiconductor

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M5M410092BRF Datasheet, PDF (75/204 Pages) Mitsubishi Electric Semiconductor – 3D-RAM (M5M410092B)

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MITSUBISHI

ELECTRONIC DEVICE GROUP

Rev. 1.03

3D-RAM (M5M410092B)

3322222222221111111111

1 0987 6543 21098765432109876543210

ROP/Blend Unit 3

ROP/Blend Unit 2

ROP/Blend Unit 1

MULTP1 Select

ROP/Adder Source Select

ROP/Blend Select

Raster Op. Select

Figure 3.18 ROP/Blend Control register data format

ROP/Blend Control Register (RBC[31:0])

This register controls the operations of the four

ROP/Blend units. Each ROP/Blend unit is

independently controlled by an 8-bit field of this

32-bit register. Bits 7 through 0 are repeated three

more times for Units 1, 2, and 3. That is, bits 15

through 8 for unit 1; bits 23 through 16 for unit 2;

and bits 31 through 24 for unit 3.

This register resets to 0303 0303h. This value

passes data unchanged from the PALU_DQ pins

through all four ROP/Blend units.

During a Stateless Data Write access, the ROP/

Blend units behave as if this register were set to

0303 0303h, regardless of its actual value.

The data format of the RBC register is illustrated

in Figure 3.18 above and explained in the

paragraph below.

â¢ Bits 8n+7 through 8n+6 select a source

for MULTP1 (Table 3.15).

Table 3.15 MULTP1 source encoding

for ROP/Blend unit n

RBC[8n+7:8n+6]

Fraction Source for ROP/

Blend Unit n

100h (1.00)

{KXn, K[8n+7:8n]}

{PALU_DXn,

PALU_DQ[8n+7:8n]}

{PALU_DX3,

PALU_DQ[31:24]}

â¢ Bit 8n+5 selects a source for ROP unit n

and for the adder in the Blend unit n. If this

bit is â0â, the data from the

PALU_DQ[8n+7:8n] is selected; if this bit is

â1â, the Constant Source register bits

K[8n+7:8n] are selected.

â¢ Bit 8n+4 configures ROP/Blend unit n. For

bit 28, the bit value of â0â sets the ROP/

Blend unit 3 in ROP and Stencil mode and

forces the output of Alpha-Saturate block to

be always OLD[31:24] regardless of the

programmed values in BLD2[29:28] and

PBC[29:28]; the bit value of â1â sets the

ROP/Blend unit 3 in Blend mode and

enable the Alpha Saturate logic . For bits 4,

12 and 20, the bit value of â0â sets the ROP/

Blend units 0, 1 and 2 in ROP mode,

respectively; the bit value of â1â sets the

ROP/Blend units 0, 1 and 2 in Blend mode,

respectively. Note that when in Blend

mode, Blend units 0, 1 and 2 will calculate

with the correct alpah saturate value only

when bit 28 of this register is also set to â1â.

Note also that the bit field St.Enable does

not specifically set the operation mode of

ALU unit 3; St. Enable enables the bit

planes 31 through 24 to be recognized as

stencil bits when ALU unit 3 is in ROP and

Stencil mode, and is ignored when ALU unit

3 is in Blend mode. (NEW rev.1.03)

â¢ Bits 8n+3 through 8n+0 select one of the

sixteen possible raster operations for Unit

n. In Table 3.16, âNEWâ represents the data

from the PALU_DQ[31:0] pins or from the

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