M5M410092BRF Datasheet, PDF (120/204 Pages) Mitsubishi Electric Semiconductor – 3D-RAM (M5M410092B)

MITSUBISHI
ELECTRONIC DEVICE GROUP
Rev. 1.03
3D-RAM (M5M410092B)
320
01
7
89
15
16 17
23
1024
240 241
247
248 249
255
The screen is 8 page groups
wide by 32 page groups high.
DRAM_A_[5:2]
A page group consists of the same page
from all four DRAM banks (A, B, C, D).
40
32
0(A)
1(B)
2(C)
3(D)
DRAM_A_[3:0]
0
16
1
2
3
20
4 8 12 16 20 24 28 32 36
5 9 13 17 21 25 29 33 37
6 10 14 18 22 26 30 34 38
7 11 15 19 23 27 31 35 39
20
16
DRAM_A_[1:0]
PALU_A_[2:1]
2
40 ¹
23
45
67
PALU_A₀
PALU_DQ_[31:0]
Each page can be divided into either 40 blocks, which can be
accessed from the Global Bus, or 16 scan lines which can be
accessed by the Video Buffer.
Blocks can be accessed in 1-pixel
words by the Pixel ALU.
20
10 1
Video Buffer
18 19
Video Buffer data is shifted out two bytes at a time on
each VID_CLK. A pixel is shifted out every two cycles.
Figure 6.3 This diagram shows how 3D-RAM maps to pixels in a single chip 320x1024x32 frame buffer. The num-
bers outside each rectangle show its dimensions in pixels.
98