M5M410092BRF Datasheet, PDF (201/204 Pages) Mitsubishi Electric Semiconductor – 3D-RAM (M5M410092B)

MITSUBISHI
ELECTRONIC DEVICE GROUP
Appendix A
Glossary
Some of the terms used in this document may be
unfamiliar to the reader, and some may have a
specific meaning in the context of this document.
For convenience, these terms are collected here
Rev. 1.03
3D-RAM (M5M410092B)
and provided with a brief definition and a
reference to the paragraphs where the terms are
explained in greater detail. This glossary list is not
intended to be exhaustive
3D-RAM
An innovative 10-Mbit cached dual-port CMOS
memory device that dramatically improves the
performance of a three-dimensional computer
graphics system with on-chip support for Z-buffer
hidden surface removal algorithm and for full
blending and logical raster operations, achieving a
peak bandwidth of 14.6 Gbytes/s and a sustained
bandwidth of 400 Mbytes/s (for the -10 speed
grade).
Blending
A computer graphics operation for simulating the
visual effect of overlapping objects with the
foreground objects being partially transparent. An
example of blending equations is that overall color
= (a) x (color of foreground object) + (1 - a) x
(color of background object), where a is the
percentage of light transmitted through the
medium of the foreground object. Each of the four
8-bit Blend units in the Pixel ALU can perform one
of the two multiplications and then the addition,
provided that the product of the other
multiplication is supplied by the rendering
controller. (Pages 10 and 26)
Block
A unit of memory organized into eight 32-bit
words. This is the unit of data movement between
a DRAM bank and the Pixel Buffer. (Pages 4
and 21)
Byte
A unit of memory containing 8 bits of data. This is
the unit of data operation for the four Blend units
in the Pixel ALU. The rendering controller can
enable or disable the writing (to 3D-RAM) or
reading (from 3D-RAM) of the individual bytes in a
word. (Pages 10, 15, and 26)
Color Buffer
The collection of memory that contains all color
bits of all pixels to be displayed on the screen.
Because the alpha information is needed for
blending operations in 3D-RAM, the alpha data
should also be stored together with the color data.
It is also popular to have overlay information
stored together with the color information to allow
fast display of 2D objects by data multiplexing in a
RADMAC chip. (Chapter 6)
Dirty Tag
A 32-bit memory in the Pixel Buffer, indicating
which of the 32 bytes in the corresponding 256-bit
block in the SRAM cache have been updated by
the Pixel ALU since the data was transferred from
the DRAM array. A “1” in a bit of Dirty Tag
indicates the corresponding byte in the SRAM
cache is newer than the data in the DRAM array.
There are eight such Dirty Tags in the Pixel
Buffer. (Page 22)
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