M5M410092BRF Datasheet, PDF (74/204 Pages) Mitsubishi Electric Semiconductor – 3D-RAM (M5M410092B)

MITSUBISHI
ELECTRONIC DEVICE GROUP
Rev. 1.03
3D-RAM (M5M410092B)
Identification Register (ID_[31:0])
The read-only Identification register contains the
manufacturer identification code (ID), part number
code, and version code in the format shown in
Figure 3.17. The manufacturer ID is 01Ch for
Mitsubishi Electronics. The part number is read as
130Ah for M5M410092B. Bit 0 is always “1”, so for
Version 0, this identifi-cation register should be
read as 0130 A039h.
Plane Mask Register (PM_[31:0])
This register affects both the Stateful Data Writes
of the Pixel ALU operations and the Masked Write
Block (MWB) of the DRAM operations. The effect
is simultaneous on both types of operations.
Therefore, the user must exercise caution to
ensure the desired plane masking is achieved
when such concurrency between the Pixel ALU
and the DRAM array is exploited. For the Stateful
Data Writes, each bit of the Plane Mask register is
a per-bit write enable for the 32-bit data entering
the Pixel Buffer. For the MWB operation, each bit
of the Plane Mask register serves as a per-bit
write enable for the 32-bit word 0 entering the
sense amplifiers of the a DRAM bank, and the
same write masking mechanism is applied to the
upper seven words of the specified Pixel Buffer
block. Figure 3.2 provides a clear illustration of
this masking relationship between the write data
and the bits of the Plane Mask register. The value
“1” means write enable; the value “0” means write
disable.
This register resets to FFFF FFFFh.
Constant Source Register (CSR_[35:0])
This register is used to store 36-bit data that is
loaded from the PALU_DQ and PALU_DX pins.
(The data extension pins PALU_DX_[3:0] are loaded
into the most significant four bits of the Constant
Source register.) The bits of this register are
commonly referred to as KX_[3:0] for the most
significant four bits and K_[31:0] for the low-order 32
bits. The four ROP/Blend units and the Dual
Compare units can individually select this register
to provide data.
This register resets to 0000 0000h.
Match Mask Register (MTM_[31:0])
This register determines which data bits
participate in the match test. Setting the bits of this
register to “1” causes the corresponding data bits
to be compared by the Match Comparison unit.
Setting the bits of this register to “0” causes the
corresponding data bits to be ignored in the match
test.
This register resets to 0000 0000h.
Magnitude Mask Register (MGM_[31:0])
This register determines which data bits
participate in the magnitude test. Setting the bits
of this register to “1” causes the corresponding
data bits to be compared by the Magnitude
Comparison unit. Setting the bits of this register
to “0” causes the corresponding data bits to be
ignored in the magnitude test.
This register resets to 0000 0000h.
3322222222221111111111
1 0987 6543 21098765432109876543210
Version
Part Number
Manufacturer ID
1
Figure 3.17 Identification register data format
58