M5M410092BRF Datasheet, PDF (147/204 Pages) Mitsubishi Electric Semiconductor – 3D-RAM (M5M410092B)

MITSUBISHI
ELECTRONIC DEVICE GROUP
Rev. 1.03
3D-RAM (M5M410092B)
Table 8.3 Pixel ALU timing parameters
M5M410092B
Symbol
Parameter
-10A
-10
-12
Unit Refer
Min Max Min Max Min Max
t_CLK Master clock MCLK cycle time
10 16000 10 ^T 16000 12 16000 ns
t₁
t_CLKH MCLK high pulse width
4—
4
—
5
—
ns
t₂
t_CLKL MCLK low pulse width
4—
4
—
5
—
ns
t₃
t_ENS PALU_EN setup time
3—
3
—
4
—
ns
t₈
t_ENH PALU_EN hold time
1.5 — 1.5 — 1.5 — ns t₉
t_OPS PALU_OP setup time
3—
3
—
4
—
ns
t₈
t_OPH PALU_OP hold time
1.5 — 1.5 — 1.5 — ns t₉
t_ADS PALU_A setup time
3—
3
—
4
—
ns
t₈
t_ADH PALU_A hold time
1.5 — 1.5 — 1.5 — ns t₉
t_WES PALU_WE setup time
3—
3
—
4
—
ns
t₈
t_WEH PALU_WE hold time
1.5 — 1.5 — 1.5 — ns t₉
t_BES PALU_BE setup time
3—
3
—
4
—
ns
t₈
t_BEH PALU_BE hold time
1.5 — 1.5 — 1.5 — ns t₉
t_CLZ MCLK to PALU_DQ low imped- 4
—
4
—
5
—
ns t₁₀
ance
t_CQ PALU_DQ access time
— 14 — 14 — 18 ns t₁₁
t_CVD PALU_DQ data valid time
4—
4
—
4
—
ns t₁₂
t_CHZ MCLK to PALU_DQ high imped- —
4
—
4
—
4
ns t₁₃
ance
t_DQS PALU_DQ, PALU_DX setup time 3
—
3
—4—
t_DQH PALU_DQ, PALU_DX hold time 1.5 — 1.5 — 1.5 —
t_PSS PASS_IN setup time
2
—
2
—
3
—
t_PSH PASS_IN hold time
1.5 — 1.5 — 1.5 —
t_CPS MCLK to valid PASS_OUT
—6
—
6—8
t_CPSV PASS_OUT data valid time
3
—
3
—
3
—
T _{tCLK = 10.0 ns except that for the alpha saturate logic tCLK = 12.0 ns.}
ns t₈
ns t₉
ns t₈
ns t₉
ns t₁₁
ns t₁₂
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