M5M410092BRF Datasheet, PDF (45/204 Pages) Mitsubishi Electric Semiconductor – 3D-RAM (M5M410092B)

MITSUBISHI
ELECTRONIC DEVICE GROUP
Rev. 1.03
3D-RAM (M5M410092B)
registers have been programmed, an “Initial Two-
Cycle Blending” operation (PALU_OP=110,
PALU_WE=1) should be performed and followed
by a Stateful Initial Data Write or Stateful Normal
Data Write operation on the same pixel location
(i.e. PALU_A with the same Block and Word
address and PALU_BE_[3:0] with the same enable
settings). During the Preblend Cycle, MULTP1
and MULTP2 are multiplied and the result is
“looped back” one stage in the pipeline. The
ADDEND is also “looped back” one stage. The
ADDEND and the multiplier output are then
available as a possible ADDEND for the next
cycle. Next, the Stateful Write is issued with the
multiplicands selected by the ROP/Blend and
Blend_2 Control registers. The ADDEND selected
by the ROP/Blend and Blend_2 registers will be
ignored. The blending occurs just as it would for a
single-cycle operation except that the ADDEND
source is chosen to be either the “looped back”
multiplier output or the “looped back” ADDEND,
based on the settings of the Preblend Control
register.
To help sort out the different sources for the
various blending factors for both the single-cycle
half blending and the two-cycle full blending,
Table 3.3 is notated with example sources of all
OpenGL blending factors. For example, all
blending factors related to the alpha component
should be selected through the MULTP2
datapath; these include DST_ALPHA,
ONE_MINUS_DST_ALPHA, and
SRC_ALPHA_SATURATE and are notated with
“M2” in their respective rows and columns. Some
source blending factors are not passed to
3D-RAM directly, but rather the product of the
source blending factor and the source color is
passed to 3D-RAM as the ADDEND term; these
include ZERO, ONE, SRC_ALPHA, and
ONE_MINUS_SRC-ALPHA.
Figure 3.4 illustrates the above description with a
simplified block diagram. The blocks labelled
“N:NN”, “N:N0”, and “NX:N” on the blending path
represent the manner in which the 8-bit Blend
units duplicate 4-bit data for the special (4,4,4,4)
16-bit color mode. Specifically, “N:NN” means that
the 4-bit data is nibble-wise duplicated to form an
8-bit data; “N:N0” means an 8-bit data is formed
by padding the lower nibble with 0000b; and
“NX:N” means a 4-bit data is produced by
truncating the lower nibble, regardless of its value.
More explanations may be found in the section on
“4-bit to 8-bit Expansion for Pixel ALU.”
Note that the special OpenGL stencil mode, which
will be described in the section on “Stencil
Modes,” uses portions of ROP/Blend unit 3 to
accomplish its functions. For simplicity, the stencil
logic is not shown in Figure 3.4 and, for the most
part, can be thought of as a separate unit. It is
important to note, however, that the stencil logic
uses portions of the blending path and therefore,
ROP/Blend unit 3 cannot be used for blending
when the OpenGL stencil mode is being used.
ROP/Blend units 0, 1 and 2 are identical, but unit
3 is slightly different because this unit typically
handles the Alpha data. The Alpha-Saturate block
shown in Figure 3.4 and Figure 3.5 is only present
in ROP/Blend unit 3. The result from the Alpha-
Saturate block is routed to all four ROP/Blend
units as a possible source of MULTP2.
For the specifics of the data multiplexing and
selections by the various register bits, refer to
Figure 3.6.
The timing diagram of an example Two-Cycle
Blend operation is presented in Figure 3.7.
29