MT46V64M8P-5BF Datasheet, PDF (90/93 Pages) Micron Technology – 512Mb: x4, x8, x16 Double Data Rate (DDR) SDRAM SDRAM Features

512Mb: x4, x8, x16 DDR SDRAM
Operations
Although not a JEDEC requirement, to provide for future functionality features, CKE
must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered and ends ^tRFC later.
Figure 54: Auto Refresh Mode
CK#
CK
CKE
Command
T0
tI_S tIH
tI_S tIH
NOP1
T1
T2
T3
CK
t_CH t_CL
Valid
PRE
NOP1
NOP1
Address
A10
BA0, BA1
DQS⁵
DQ5
DM5
All banks
One bank
tI_S tIH
Bank(s)4
tRP
T4
((
Ta0
Ta1 ₍₍
Tb0
Tb1
Tb2
))
))
((
((
))
))
((
((
))
))
((
(( ^Valid
))
))
((
((
AR
))
((
NOP1,2
AR3
))
((
NOP1,2
NOP1
ACT
))
))
((
((
))
))
((
((
RA
))
))
((
((
))
))
((
((
RA
))
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tRF_C
((
))
((
BA
))
((
))
((
))
((
))
((
))
((
))
((
))
tRF_C
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock-positive transitions.
2. NOP or COMMAND INHIBIT are the only commands allowed until after ^tRFC time; CKE must
be active during clock-positive transitions.
3. The second AUTO REFRESH is not required and is only shown as an example of two back-to-
back AUTO REFRESH commands.
4. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(that is, must precharge all active banks).
5. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for the operations shown.
SELF REFRESH
When in the self refresh mode, the DDR SDRAM retains data without external clocking.
The DLL is automatically disabled upon entering SELF REFRESH and is automatically
enabled upon exiting SELF REFRESH (a DLL reset and 200 clock cycles must then occur
before a READ command can be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH. V_REF voltage is also required for the full duration of SELF
REFRESH.
The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK
and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for ^tXSNR because time is required for the
completion of any internal refresh in progress. A simple algorithm for meeting both
refresh and DLL requirements is to apply NOPs for ^tXSRD time, then a DLL RESET (via
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
90
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