MT46V64M8P-5BF Datasheet, PDF (86/93 Pages) Micron Technology – 512Mb: x4, x8, x16 Double Data Rate (DDR) SDRAM SDRAM Features

512Mb: x4, x8, x16 DDR SDRAM
Operations
Figure 50: WRITE – DM Operation
CK#
CK
CKE
Command
Address
A10
BA0, BA1
DQS
DQ5
DM
T0
tIS tIH
tIS tIH
NOP1
T1
tCK
T2
T3
tCH tCL
T4
T4n
T5
T5n
T6
ACT
tIS tIH
Row
NOP1
Row
tIS tIH
Bank x
tRCD
tRAS
WRITE2
Col n
tIS tIH
3
NOP1
Bank x
tDQSS _(NOM)
NOP1
NOP1
tWPRES tWPRE
DI
b
tDQSL tDQSH tWPST
T7
T8
NOP1
PRE
tWR
All banks
One bank
Bank x⁴
tRP
tDS
tDH
Transitioning Data
Don’t Care
Notes:
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T8.
5. DI b = data-in from column b; subsequent elements are provided in the programmed order.
6. See Figure 51 on page 87 for detailed DQ timing.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
86
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