MT46V64M8P-5BF Datasheet, PDF (71/93 Pages) Micron Technology – 512Mb: x4, x8, x16 Double Data Rate (DDR) SDRAM SDRAM Features

Figure 35: Bank READ – Without Auto Precharge
CK#
CK
CKE
Command
T0
t_IS t_IH
t_IS t_IH
NOP1
Address
A10
BA0, BA1
T1
T2
T3
T4
t_CK
t_CH t_CL
ACT
t_IS t_IH
Row
NOP1
Row
t_IS t_IH
Bank x
t_RCD
tRAS3
t_RC
READ2
Col n
t_IS t_IH
4
NOP1
Bank x
CL = 2
DM
512Mb: x4, x8, x16 DDR SDRAM
Operations
T5 T5n T6 T6n T7
T8
PRE3
NOP1
All banks
One bank
Bank x⁵
t_RP
NOP1
ACT
Row
Row
Bank x
Case 1: ^tAC (MIN) and ^tDQSCK (MIN)
DQS
DQ
t_RPRE
t_{DQSCK (MIN)}
t_{LZ (MIN)}
t_{LZ (MIN)}
DO
n
t_{AC (MIN)}
t_RPST
Case 2: ^tAC (MAX) and ^tDQSCK (MAX)
DQS
t_RPRE t_{DQSCK (MAX)}
t_RPST
DQ
DO
n
t_{AC (MAX)}
t_{HZ (MAX)}
Notes:
Transitioning Data
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
2. BL = 4.
3. The PRECHARGE command can only be applied at T5 if ^tRAS (MIN) is met.
4. Disable auto precharge.
5. “Don’t Care” if A10 is HIGH at T5.
6. DO n (or b) = data-out from column n (or column b); subsequent elements are provided in
the programmed order.
7. Refer to Figure 36 on page 72, Figure 37 on page 73, and Figure 38 on page 74 for detailed
DQS and DQ timing.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
71
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