MT46V64M8P-5BF Datasheet, PDF (48/93 Pages) Micron Technology – 512Mb: x4, x8, x16 Double Data Rate (DDR) SDRAM SDRAM Features

512Mb: x4, x8, x16 DDR SDRAM
Commands
2. This table describes alternate bank operation, except where noted (that is, the current state
is for bank n, and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
• Idle: The bank has been precharged, and ^tRP has been met.
• Row active: A row in the bank has been activated, and ^tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
• Read: A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
• Read with auto precharge enabled: See note 3a below.
• Write with auto precharge enabled: See note 3a below.
a. The read with auto precharge enabled or write with auto precharge enabled states
can each be broken into two parts: the access period and the precharge period. For
read with auto precharge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with the earliest possible
PRECHARGE command that still accesses all of the data in the burst. For write with
auto precharge, the precharge period begins when ^tWR ends, with ^tWR measured as
if auto precharge was disabled. The access period starts with registration of the com-
mand and ends where the precharge period (or ^tRP) begins. This device supports
concurrent auto precharge such that when a read with auto precharge is enabled or
a write with auto precharge is enabled, any command to other banks is allowed, as
long as that command does not interrupt the read or write data transfer already in
process. In either case, all other related limitations apply (for example, contention
between read data and write data must be avoided).
b. The minimum delay from a READ or WRITE command with auto precharge enabled,
to a command to a different bank is summarized in Table 34.
Table 34: Command Delays
CL_RU = CL rounded up to the next integer
From
Command
WRITE with auto
precharge
READ with auto
precharge
To Command
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE
ACTIVE
Minimum Delay
with Concurrent Auto Precharge
[1 + (BL/2)] × ^tCK + ^tWTR
(BL/2) × ^tCK
1 ^tCK
1 ^tCK
(BL/2) × ^tCK
[CL_RU + (BL/2)] × ^tCK
1 ^tCK
1 ^tCK
4. AUTO REFRESH and LMR commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank
represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the “Command/Action” column include READs or WRITEs with
auto precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM masking.
9. A WRITE command may be applied after the completion of the READ burst; otherwise, a
BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE com-
mand.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 512Mb DDR: Rev. Q; Core DDR Rev. E 7/11 EN
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