MT46V4M32 Datasheet, PDF (9/66 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

lected by A1-Ai when the burst length is set to two, by
A2-Ai when the burst length is set to four and by A3-Ai
when the burst length is set to eight (where Ai is the
most significant column address bit for a given con-
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.
CK#
CK
COMMAND
DQS
Figure 2
CAS Latency
T0
T1
T2 T2n T3 T3n
READ
NOP
NOP
NOP
CL = 2
DQ
CK#
CK
COMMAND
T0
READ
DQS
T1
T2
NOP
NOP
CL = 3
T3 T3n
NOP
DQ
Burst Length = 4 in the cases shown
Shown with nominal ^tAC and nominal ^tDSDQ
TRANSITIONING DATA
DON’T CARE
ADVANCE
128Mb: x32
DDR SDRAM
SPEED
-33
-4
-5
Table 2
CAS Latency
ALLOWABLE OPERATING
FREQUENCY (MHz)
CL = 5
CL = 4
CL = 3
≤ 300
≤ 250
−
−
≤ 250
≤ 200
−
−
≤ 200
Read Latency
The READ latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2, 3, 4 or 5 clocks, as shown in Figure 2.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available nominally
coincident with clock edge n + m. Table 2 indicates the
operating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7-A11 each
set to zero, and bits A0-A6 set to the desired values. A
DLL reset is initiated by issuing a MODE REGISTER
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
9
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