MT46V4M32 Datasheet, PDF (42/66 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

ADVANCE
128Mb: x32
DDR SDRAM
CLOCK INPUT OPERATING CONDITIONS
(Notes: 1–5, 15, 16, 30; notes appear on pages 46–49) (0°C ≤ T_A ≤+ 70°C; VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V)
PARAMETER/CONDITION
Clock Input Mid-Point Voltage; CK and CK#
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
SYMBOL
MIN
VMP(DC)
1.15
VIN(DC)
-0.3
VID(DC)
0.36
VID(AC)
0.7
VIX(AC) 0.5 x VDDQ - 0.2
MAX
1.35
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 x VDDQ + 0.2
UNITS
V
V
V
V
V
NOTES
6, 9
6
6, 8
8
9
2.80V
CK#
Figure 27
SSTL_2 Clock Input
Maximum Clock Level⁵
1.45V
1.25V
1.05V
X
X
VMP (DC)¹ _{VIX (AC)}2
3
VID (DC)
4
VID (AC)
CK
- 0.30V
Minimum Clock Level⁵
NOTE:
1. This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of VDDQ.
2. CK and CK# must cross in this region.
3. CK and CK# must meet at least VID(DC) min when static and is centered around VMP(DC)
4. CK and CK# must have a minimum 700mv peak to peak swing.
5. CK or CK# may not be more positive than VDDQ + 0.3V or more negative than Vss - 0.3V.
6. For AC operation, all DC clock requirements must also be satisfied.
7. Numbers in diagram reflect nominal values.
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
42
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©2002, Micron Technology, Inc.