MT46V4M32 Datasheet, PDF (29/66 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

CK#
CK
COMMAND
T0
WRITE
ADDRESS
Bank a,
Col b
t_{DQSS (NOM)}
DQS
t_DQSS
DQ
DM
Figure 19
WRITE to READ – Uninterrupting
T1 T1n T2 T2n T3
T4
NOP
NOP
NOP
READ
t_WTR
Bank a,
Col n
DI
b
t_{DQSS (MIN)}
DQS
DQ
DM
t_DQSS
DI
b
t_{DQSS (MAX)}
DQS
t_DQSS
DQ
DI
b
DM
ADVANCE
128Mb: x32
DDR SDRAM
T5
T6 T6n
NOP
NOP
CL = 2
DI
n
CL = 2
DI
n
CL = 2
DI
n
DON T CARE
TRANSITIONING DATA
NOTE: 1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. An uninterrupted burst of 4 is shown.
4. ^tWTR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same bank. However, the READ and WRITE commands may be
to different devices, in which case ^tWTR is not required and the READ command could be applied earlier.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
29
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©2002, Micron Technology, Inc.