MT46V4M32 Datasheet, PDF (39/66 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

ADVANCE
128Mb: x32
DDR SDRAM
TRUTH TABLE 4 – CURRENT STATE BANK n – COMMAND TO BANK m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE CS# RAS# CAS# WE#
Any
HXXX
L HHH
Idle
XXXX
Row
L L HH
Activating,
LHLH
Active, or
LHL L
Precharging L L H L
Read
L L HH
(Auto-
LHLH
Precharge
LHL L
Disabled)
L LHL
Write
L L HH
(Auto-
LHLH
Precharge
LHL L
Disabled)
L LHL
Read
L L HH
(With Auto- L H L H
Precharge)
LHL L
L LHL
Write
L L HH
(With Auto- L H L H
Precharge)
LHL L
L LHL
COMMAND/ACTION
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
NOTES
7
7
7
7, 9
7, 8
7
7
7, 9
7
7
NOTE:
1. This table applies when CKE_n-1 was HIGH and CKE_n is HIGH (see Truth Table 2) and after ^tXSNR has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and
the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state
that the given command is allowable). Exceptions are covered in the notes below.
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
39
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©2002, Micron Technology, Inc.