MT46V4M32 Datasheet, PDF (1/66 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

DOUBLE DATA RATE
(DDR) SDRAM
ADVANCE^‡
128Mb: x32
DDR SDRAM
MT46V4M32 - 1 Meg x 32 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
FEATURES
• VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Reduced and matched output drive options
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data
• Programmable burst lengths: 2, 4, 8, or full page
• 32ms, 4,096-cycle auto refresh
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 2.5V I/O (SSTL_2 compatible)
• DQS per byte on the FBGA package
• 1.8V VDDQ option for FBGA package
• ^tRAS lockout
OPTIONS
MARKING
• Configuration
4 Meg x 32 (1 Meg x 32 x 4 banks)
4M32
• IO Voltage
2.5V VDDQ
None
1.8V VDDQ
V1
• Plastic Packages
100-pin TQFP (0.65mm lead pitch)
LG
12mm x 12mm FBGA
FK
• Timing - Cycle Time
300 MHz @ CL = 5
-33¹
250 MHz @ CL = 4
-4¹
200 MHz @ CL = 3
-5
Note: 1. -4 and -33 speed grades are only available in the FBGA package
Part Number Example:
MT46V4M32V1FK-33
128Mb (x32) DDR SDRAM PART NUMBER
PART NUMBER
MT46V4M32LG
ARCHITECTURE
4 Meg x 32
PIN ASSIGNMENT (TOP VIEW)
100-Pin TQFP
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DM0
DM2
WE#
CAS#
RAS#
CS#
BA0
BA1
10099 98 97 96 95 94 93 9291 90 89 88 87 86 8584 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 3940 41 42 43 44 45 4647 48 49 50
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
VREF
DM3
DM1
CK
CK#
CKE
NC/MCL
A8/AP
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
4 Meg x 32
1 Meg x 32 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
256 (A0-A7)
KEY TIMING PARAMETERS
SPEED
CLOCK RATE
DATA-OUT ACCESS DQS-DQ
GRADE CL = 5¹ CL = 4¹ CL = 3¹ WINDOW² WINDOW SKEW
-33 300 MHz 250 MHz -
0.685ns ±0.6ns +0.40ns
-4
- 250 MHz 200 MHz 0.950ns ±0.7ns +0.45ns
-5
-
- 200 MHz 1.400ns ±0.7ns +0.45ns
1. CL = CAS (Read) Latency
2. Minimum clock rate @ max CL
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
1
©2002, Micron Technology, Inc.
‡_{PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY}
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.