MT46V4M32 Datasheet, PDF (58/66 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

AUTO REFRESH MODE
ADVANCE
128Mb: x32
DDR SDRAM
CK#
CK
CKE
COMMAND¹
T0
t_IS t_IH
t_IS t_IH
NOP ²
T1
T2
T3
t_CK
t_CH t_CL
VALID
PRE
NOP ²
NOP ²
A0-A7, A9-A11
A8¹
BA0, BA1¹
DQS⁴
DQ⁴
DM⁴
ALL BANKS
ONE BANK
t_IS t_IH
Bank(s) ³
tRP
T4
Ta0
((
Ta1
((
Tb0
Tb1
Tb2
))
))
((
((
))
))
((
((
))
))
((
((
VALID
))
))
((
((
AR
))
((
NOP ²
AR ⁵
))
((
NOP2
NOP2
ACT
))
))
((
((
))
))
((
((
RA
))
))
((
((
))
))
((
((
RA
))
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tRFC
((
))
((
BA
))
((
))
((
))
((
))
((
))
((
))
((
))
tRFC 5
NOTE:
1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
3. Don t Care if A8 is HIGH at this point; A8 must be HIGH if more than one bank is active (i.e., must precharge all active banks).
4. DM, DQ and DQS signals are all Don t Care /High-Z for operations shown.
5. The second AUTO REFRESH is not required and is only shown as an example of two back-to-back AUTO REFRESH commands.
DON T CARE
TIMING PARAMETERS
SYMBOL
t_CH
t_CL
t_{CK (5)}
t_{CK (4)}
-33
MIN MAX
0.45 0.55
0.45 0.55
3.3
8
4
8
-4
MIN MAX
0.45 0.55
0.45 0.55
-
-
4
8
-5
MIN MAX
0.45 0.55
0.45 0.55
-
-
-
-
UNITS
t_CK
t_CK
ns
ns
SYMBOL
t_{CK (3)}
t_IH
t_IS
t_RFC
t_RP
-33
MIN MAX
-
-
0.9
0.9
62
16
-4
MIN MAX
-
-
0.9
0.9
62
16
-5
MIN MAX
5
8
0.9
0.9
62
20
UNITS
ns
ns
ns
ns
ns
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
58
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©2002, Micron Technology, Inc.