MT46V4M32 Datasheet, PDF (28/66 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

CK#
CK
COMMAND
T0
WRITE
ADVANCE
128Mb: x32
DDR SDRAM
Figure 18
Random WRITE Cycles
T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n
WRITE
WRITE
WRITE
WRITE
NOP
ADDRESS
DQS
DQ
DM
Bank,
Col b
Bank,
Col x
t_{DQSS (NOM)}
Bank,
Col n
Bank,
Col a
Bank,
Col g
DI
DI
DI
DI
DI
DI
DI
DI
DI
DI
b
b'
x
x'
n
n'
a
a'
g
g'
DON’T CARE
TRANSITIONING DATA
NOTE: 1. DI b, etc. = data-in for column b, etc.
2. b', etc. = the next data-in following DI b, etc., according to the programmed burst order.
3. Programmed burst length = 2. For 4, or 8 the burst is terminated.
4. Each WRITE command may be to any bank.
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
28
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©2002, Micron Technology, Inc.