MT40A512M8RH-075E Datasheet, PDF (79/365 Pages) Micron Technology – DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Write Leveling
Figure 22: Write Leveling Exit
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
CK_c
CK_t
Command DES
DES
DES
DES
DES
DES
DES
Address
ODT
R_{TT(DQS_t)}
R_{TT(DQS_c)}
DQS_t,
DQS_c
R_TT(DQ)
DQ¹
R_TT(NON)
t_WLO
t_IS
ODTL (OFF)
t_{ADC (MIN)}
t_{ADC (MAX)}
result = 1
Tc2
DES
MR1
Td0
Td1
DES
t_MRD
Valid
Valid
t_MOD
R_TT(Park)
Te0
DES
Te1
Valid
Valid
Undefined Driving Mode
Transitioning
Time Break
Don’t Care
Notes: 1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS signals capturing CK_t
HIGH just after the T0 state.
2. See previous figure for specific ^tWLO timing.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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