MT40A512M8RH-075E Datasheet, PDF (223/365 Pages) Micron Technology – DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 166: Rx Mask DQ-to-DQS Timings
DQS, DQs Data-In at DRAM Ball
Rx Mask
DQS_c
DQS_t
0.5 × TdiVW 0.5 × TdiVW
DQS, DQs Data-In at DRAM Ball
Rx Mask – Alternative View
DQS_c
DQS_t
0.5 × TdiVW 0.5 × TdiVW
DRAMa
DQx–z
Rx Mask
TdiVW
DRAMa
DQx–z
Rx Mask
TdiVW
DRAMb
DQy
DRAMb
DQz
DRAMc
DQz
t_DQS2DQ
Rx Mask
t_DQ2DQ
Rx Mask
t_DQS2DQ
Rx Mask
t_DQ2DQ
t_{DQS2DQ +0.5 × TdiVW}
DRAMb
DQy
DRAMb
DQz
t_DQ2DQ
Rx Mask
T_diVW
Rx Mask
T_diVW
t_DQ2DQ
t_{DQS2DQ +0.5 × TdiVW}
DRAMc
DQz
t_DQ2DQ
Rx Mask
T_diVW
DRAMc
DQy
Rx Mask
DRAMc
DQy
Rx Mask
T_diVW
t_DQ2DQ
Notes:
1. DQx represents an optimally centered mask.
DQy represents earliest valid mask.
DQz represents latest valid mask.
2. DRAMa represents a DRAM without any DQS/DQ skews.
DRAMb represents a DRAM with early skews (negative ^tDQS2DQ).
DRAMc represents a DRAM with delayed skews (positive ^tDQS2DQ).
3. This figure shows the skew allowed between DRAM-to-DRAM and between DQ-to-DQ
for a DRAM. Signals assume data is center-aligned at DRAM latch.
TdiPW is not shown; composite data-eyes shown would violate TdiPW.
V_{CENTDQ,midpoint} is not shown but is assumed to be midpoint of V_diVW.
The previous figure shows the basic Rx mask requirements. Converting the Rx mask re-
quirements to a classical DQ-to-DQS relationship is shown in the following figure. It
should become apparent that DRAM write training is required to take full advantage of
the Rx mask.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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