MT40A512M8RH-075E Datasheet, PDF (267/365 Pages) Micron Technology – DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 87: Single-Ended Input Slew Rates
Parameter
Single-ended input slew rate – CA
Symbol
SR_CA
Min
1.0
Max
7.0
Unit
V/ns
Note
1, 2, 3, 4
Notes:
1. For input except RESET_n.
2. V_REF = V_REFCA(DC).
3. ^tIS/^tIH timings assume SR_CA = 1V/ns.
4. Measured between V_IH(AC) and V_IL(AC) for falling edges and between V_IL(AC) and V_IH(AC)
for rising edges
Figure 208: Single-Ended Input Slew Rate Definition
TF_se
TR_se
VIH(DC)
VIH(AC)
VREFCA
VIL(AC)
VIL(DC)
Command, Control, and Address Setup, Hold, and Derating
The total ^tIS (setup time) and ^tIH (hold time) required is calculated to account for slew
rate variation by adding the data sheet ^tIS (base) values, the V_IL(AC)/V_IH(AC) points, and
t_{IH (base) values, the VIL(DC)/VIH(DC) points; to the Δ}t_{IS and Δ}t_{IH derating values, re-}
spectively. The base values are derived with single-end signals at 1V/ns and differential
clock at 2 V/ns. Example: ^tIS (total setup time) = ^tIS (base) + Δ^tIS. For a valid transition,
the input signal has to remain above/below V_IH(AC)/V_IL(AC) for the time defined by ^tVAC.
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V_IH(AC)/V_IL(AC) at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach
V_IH(AC)/V_IL(AC). For slew rates that fall between the values listed in derating tables, the
derating values may be obtained by linear interpolation.
Setup (^tIS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V_IL(DC)max and the first crossing of V_IH(AC)min that does not ring back be-
low V_IH(DC)min . Setup (^tIS) nominal slew rate for a falling signal is defined as the slew
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