MT40A512M8RH-075E Datasheet, PDF (73/365 Pages) Micron Technology – DDR4 SDRAM

4Gb: x4, x8, x16 DDR4 SDRAM
DLL-On/Off Switching Procedures
DLL-Off to DLL-On Procedure
To switch from DLL-off to DLL-on (with required frequency change) during self refresh:
1. Starting from the idle state (all banks pre-charged, all timings fulfilled, and DRAM
ODT resistors (R_TT(NOM)) must be in High-Z before self refresh mode is entered.)
2. Enter self refresh mode; wait until ^tCKSRE/^tCKSRE_PAR are satisfied.
3. Change frequency (following the guidelines in the Input Clock Frequency Change
section).
4. Wait until a stable clock is available for at least ^tCKSRX at device inputs.
5. Starting with the SELF REFRESH EXIT command, CKE must continuously be regis-
tered HIGH until ^tDLLK timing from the subsequent DLL RESET command is sat-
isfied. In addition, if any ODT features were enabled in the mode registers when
self refresh mode was entered, the ODT signal must continuously be registered
LOW or HIGH until ^tDLLK timing from the subsequent DLL RESET command is
satisfied. If R_TT(NOM) disabled in the mode registers when self refresh mode was
entered, the ODT signal is "Don't Care."
6. Wait ^tXS or ^tXS_ABORT, depending on bit 9 in MR4, then set MR1 bit A0 to 0 to en-
able the DLL.
7. Wait ^tMRD, then set MR0 bit A8 to 1 to start DLL reset.
8. Wait ^tMRD, then set mode registers with appropriate values; an update of CL,
CWL, and WR may be necessary. After ^tMOD is satisfied from any proceeding MRS
command, a ZQCL command can also be issued during or after ^tDLLK.
9. Wait for ^tMOD to complete. Remember to wait ^tDLLK after DLL RESET before ap-
plying any command requiring a locked DLL. In addition, wait for ^tZQoper in case
a ZQCL command was issued.
The device is ready for the next command.
Figure 18: DLL Switch Sequence from DLL-Off to DLL-On
Ta
CK_c
CK_t
Note 1
CKE
Tb0
Tb1
Tc
t_CKSRE/t_{CKSRE_PAR}
t_{IS tCPDED}
Command
MRS²
SRE³
DES
Td
Te0
Te1
Tf
Tg
Th
Note 4
t_CKSRX5
Valid
t_{XS_ABORT}
SRX⁶
Valid⁷
Valid
Valid⁷
Valid
Valid⁷
Address
ODT
t_RP
t_IS
t_CKESR/t_{CKESR_PAR}
Valid
t_XS
Valid
Valid
t_MRD
Valid
Enter self refresh
Notes: 1. Starting in the idle state.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
73
Exit self refresh
Time Break
Don’t Care
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